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AM79C965A
PCnetTM-32 Single-Chip 32-Bit Ethernet Controller
DISTINCTIVE CHARACTERISTICS
s Single-chip Ethernet controller for 486 and Video Electronics Standards Association (VESA) local buses s Supports ISO 8802-3 (IEEE/ANSI 802.3) and Ethernet standards s Direct interface to the 486 local bus or VESA VL-Bus s Enhanced burst mode with support for Am486TM burst read/write operations s Software-compatible with AMD's Am7990 LANCE, Am79C90 C-LANCE, Am79C960 PCnet-ISA, Am79C961 PCnet-ISA+, Am79C961A PCnet-ISA II, Am79C970A PCnet-PCI II, and Am79C900 ILACCTM register and descriptor architecture s Compatible with Am2100/Am1500T and Novell NE2100/NE1500 driver software s High-performance Bus Master architecture with integrated DMA buffer management unit for low CPU and bus utilization s Built-in byte-swap logic supports both big and little endian byte alignment s Microwire EEPROM interface supports jumperless design s Single +5 V power supply operation s Low-power, CMOS design with sleep modes allows reduced power consumption for critical battery-powered applications and Green PCs s Look-Ahead Packet Processing (LAPP) allows protocol analysis to begin before end of receive frame s Integrated Manchester encoder/decoder s Individual 136-byte transmit and 128-byte receive FIFOs provide frame buffering for increased system latency tolerance and support the following features: --Automatic retransmission with no FIFO reload --Automatic receive stripping and transmit padding (individually programmable) --Automatic runt packet rejection --Automatic deletion of received collision frames s JTAG Boundary Scan (IEEE 1149.1) test access port interface for board-level production test s Provides integrated attachment unit interface (AUI) and 10BASE-T transceiver with automatic port selection s Automatic twisted-pair receive polarity detection and automatic correction of the receive polarity s Optional byte padding to long-word boundary on receive s Dynamic transmit FCS generation programmable on a frame-by-frame basis s Internal/external loopback capabilities s Supports the following types of network interfaces: --AUI to external 10BASE-2, 10BASE-5, 10BASE-T or 10BASE-F MAU --Internal 10BASE-T transceiver with Smart Squelch to twisted-pair medium s Supports LANCE/C-LANCE/PCnet-ISA general purpose serial interface (GPSI) s 160-pin PQFP package
GENERAL DESCRIPTION
The PCnet-32 single-chip 32-bit Ethernet controller is a highly integrated Ethernet system solution designed to address high-performance system application requirements. It is a flexible bus-mastering device that can be used in any networking application, including networkready PCs, printers, fax modems, and bridge/router designs. The bus-master architecture provides high data throughput in the system and low CPU and bus utilization. The PCnet-32 controller is fabricated with AMD's advanced low-power CMOS process to provide low operating and standby current for power-sensitive applications.
Publication# 18219 Rev: D Amendment/0 Issue Date: August 2000
The PCnet-32 controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus interface unit, a DMA buffer management unit, an ISO 8802-3 (IEEE/ANSI 802.3)-defined media access control (MAC) function, individual 136-byte transmit and 128-byte receive FIFOs, an ISO 8802-3 (IEEE/ANSI 802.3)-defined attachment unit interface (AUI) and twisted-pair transceiver medium attachment unit (10BASE-T MAU), and a microwire EEPROM interface. The PCnet-32 controller is also register-compatible with the LANCE (Am7990) Ethernet controller, the CLANCE (Am79C90) Ethernet controller, the ILACC (Am79C900) Ethernet controller, and all Ethernet controllers in the PCnet family, including the PCnet-ISA controller (Am79C960), the PCnet-ISA+ controller (Am79C961), PCnet-ISA II (Am79C961A), and the PCnet-PCI II controller (Am79C970A). The buffer mana g e m e n t u n i t s u p p o r t s t h e L A N C E , I L AC C (Am79C900), and PCnet descriptor software models. The PCnet-32 controller is software-compatible with Novell NE2100 and NE1500 Ethernet adapter card architectures. In addition, a Sleep function has been incorporated to provide low standby current, which is essential for notebooks and Green PCs. The 32-bit demultiplexed bus interface unit provides a direct interface to the VESA VL-Bus and 486 series microprocessors, simplifying the design of an Ethernet node in a PC system. With its built-in support for both
little and big endian byte alignment, this controller also addresses proprietary non-PC applications. Key PCnet-32 configuration parameters, including the unique IEEE physical address, can be read from an external non-volatile memory (serial EEPROM) immediately following system reset. In addition, the I/O location at which the internal registers are accessed may be stored in the EEPROM, allowing the software model of the device to be located appropriately in system I/O space during system initialization. The controller has the capability to select automatically either the AUI port or the twisted-pair transceiver. Only one interface is active at any one time. The individual transmit and receive FIFOs reduce system overhead, providing sufficient latency during frame transmission and reception, and minimizing intervention during nor mal networ k error recover y. The integrated Manchester encoder/decoder (MENDEC) eliminates the need for an external serial interface adapter (SIA) in the node system. The built-in general purpose serial interface (GPSI) allows the MENDEC to be bypassed. In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity, or jabber status. The PCnet-32 controller also provides an external address detection interface (EADI) to allow external hardware address filtering in inter-networking applications.
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AM79C965A
ORDERING INFORMATION Standard Products:
AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below.
AM79C965A
K
C
\W
ALTERNATIVE PACKAGE OPTION \W = Trimmed and Formed in a Tray (PQJ160)
OPTIONAL PROCESSING Blank = Standard Processing
OPERATING CONDITIONS C = Commercial (0C to +70C)
PACKAGE TYPE (per Prod. Nomenclature/16-038) K = Plastic Quad Flat Pack (PQR160)
SPEED Not Applicable DEVICE NUMBER/DESCRIPTION AM79C965A PCnet-32 Single-Chip 32-Bit Ethernet Controller
Valid Combinations AM79C965A KC, KC\W
Valid Combinations
Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
AM79C965A
3
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 BLOCK DIAGRAM: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CONNECTION DIAGRAM: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PIN DESIGNATIONS: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DRIVER TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PIN DESCRIPTION: VESA VL-BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CONFIGURATION PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CONFIGURATION PIN SETTINGS SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PIN CONNECTIONS TO VDD OR VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VESA VL-BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MICROWIRE EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ATTACHMENT UNIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TWISTED PAIR INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 GENERAL PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 POWER SUPPLY PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VESA VL-BUS / LOCAL BUS PIN CROSS-REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 BLOCK DIAGRAM: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CONNECTION DIAGRAM: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PIN DESIGNATIONS: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LISTED BY PIN NUMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LISTED BY PIN NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LISTED BY GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DRIVER TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PIN DESCRIPTION: 486 LOCAL BUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CONFIGURATION PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CONFIGURATION PIN SETTINGS SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PIN CONNECTIONS TO VDD OR VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LOCAL BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 BOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MICROWIRE EEPROM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ATTACHMENT UNIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 TWISTED PAIR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 EXTERNAL ADDRESS DETECTION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 GENERAL PURPOSE SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 POWER SUPPLY PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 BASIC FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SYSTEM BUS INTERFACE FUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SOFTWARE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 BUS ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 BUS MASTER DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INITIALIZATION BLOCK DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DESCRIPTOR DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 FIFO DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 LINEAR BURST DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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AM79C965A
SLAVE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 VESA VL-BUS MODE TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 BUS MASTER AND BUS SLAVE DATA BYTE PLACEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 BUFFER MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 RE-INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 BUFFER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DESCRIPTOR RINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DESCRIPTOR RING ACCESS MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 POLLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 TRANSMIT DESCRIPTOR TABLE ENTRY (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 RECEIVE DESCRIPTOR TABLE ENTRY (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TRANSMIT AND RECEIVE MESSAGE DATA ENCAPSULATION . . . . . . . . . . . . . . . . . . . . . . . . 91 MEDIA ACCESS MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 MANCHESTER ENCODER/DECODER (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 EXTERNAL CRYSTAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 EXTERNAL CLOCK DRIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MENDEC TRANSMIT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TRANSMITTER TIMING AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 RECEIVER PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 INPUT SIGNAL CONDITIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 CLOCK ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PLL TRACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 CARRIER TRACKING AND END OF MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DATA DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 JITTER TOLERANCE DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ATTACHMENT UNIT INTERFACE(AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DIFFERENTIAL INPUT TERMINATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 COLLISION DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TWISTED-PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TWISTED PAIR TRANSMIT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 TWISTED PAIR RECEIVE FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 POLARITY DETECTION AND REVERSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 TWISTED PAIR INTERFACE STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 COLLISION DETECT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION . . . . . . . . . . . . . . . . . . . . . . 99 JABBER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10BASE-T INTERFACE CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 BOUNDARY SCAN CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SUPPORTED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 INSTRUCTION REGISTER AND DECODING LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 OTHER DATA REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 EADI (EXTERNAL ADDRESS DETECTION INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 GENERAL PURPOSE SERIAL INTERFACE (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 POWER SAVINGS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SOFTWARE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I/O REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 HARDWARE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PCNET-32 CONTROLLER MASTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SLAVE ACCESS TO I/O RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 EEPROM MICROWIRE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 AM79C965A 5
TRANSMIT OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMIT FUNCTION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTOMATIC PAD GENERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMIT FCS GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMIT EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE FUNCTION PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUTOMATIC PAD STRIPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE FCS CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE EXCEPTION CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LOOPBACK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H_RESET, S_RESET AND STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SETUP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RUNNING REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAP REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONTROL AND STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUS CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INITIALIZATION BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RLEN AND TLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RDRA AND TDRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LADRF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE DESCRIPTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMD2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMIT DESCRIPTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMD0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMD3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSRS -- CONTROL AND STATUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BCR -- BUS CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESTIMATED OUTPUT VALID DELAY VS. LOAD CAPACITANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSTEM BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AM79C965A
117 117 118 118 118 119 119 119 120 120 120 121 122 122 122 123 124 124 124 125 125 152 170 171 172 172 173 173 173 173 173 174 175 175 175 176 177 178 179 179 183 184 184 184 187 187 189 190 191 192 193 193 195 195 196 201 203 206
EADI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PQR-160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Plastic Quad Flat Pack Trimmed and Formed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX A: LOGICAL ADDRESS FILTERING FOR ETHERNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX B: RECOMMENDATION FOR POWER AND GROUND DECOUPLING . . . . . . . . . . . . . . . . . APPENDIX C: ALTERNATIVE METHOD FOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX D: INTRODUCTION OF THE LOOK-AHEAD PACKET PROCESSING (LAPP) CONCEPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX E: AM79C965A PCNET-32 SILICON ERRATA REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . .
207 208 208 208 A-1 B-1 C-1 D-1 E-1
AM79C965A
7
BLOCK DIAGRAM: VESA VL-BUS MODE
LCLK BE0- BE3 ADS BRDY WBACK BLAST LRDY RDYRTN M/IO D/C W/R INTR1-INTR4 LREQ LREQI LGNT LGNTO SLEEP LDEV LEADS LBS16 RESET ADR2-ADR31 DAT0-DAT31 VLBEN LB/VESA
Rcv FIFO
802.3 MAC Core Manchester Encoder/ Decoder (PLS) and AUI Port CI+/-D DI+/-D XTAL1 XTAL2 DO+/-D
RXD+/-D
VESA VL-Bus Interface Unit
Xmt FIFO
10BASE-T MAU
TXD+/-D TXP+/-D
LNKST
FIFO Control
Microwire, LED, and JTAG Control Buffer Management Unit
EEDI EECS EESK EEDO SHFBUSY LED1-LED3 TCK TDI TMS TDO
18219-1
8
AM79C965A
CONNECTION DIAGRAM: VESA VL-BUS MODE
NC SHFBUSY DVSSN15 EECS SLEEP EESK/LED1/SFBD EEDI/LNKST LB/VESA EEDO/LEDPRE3/SRD INTR1 ADR18 ADR19 ADR20 DVSSN14 ADR21 ADR22 ADR23 ADR24 DVDDO5 ADR25 ADR26 DVSSN13 ADR27 ADR28 DVSS4 DVDD3 ADR29 ADR30 ADR31 AVDD2 CI+ CI DI+ DI AVDD1 DO+ DO AVSS1 NC NC NC LED2/SRDCLK DVSSN1 ADR17 ADR16 ADR15 ADR14 DVDDO1 ADR13 ADR12 DVSSN2 ADR11 ADR10 ADR9 ADR8 ADR7 DVSSN3 ADR6 ADR5 DVSSPAD ADR4 ADR3 DVSSN4 ADR2 LBS16 DVDD1 LEADS DVSSCLK LCLK DVDDCLK VLBEN BLAST LGNT BRDY DVDDO2 LREQ DVSS1 LDEV NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXD-D TXP-D AVDD4 RXD+ RXD-D DVSS3 JTAGSEL INTR2/EAR INTR3/TDI DVSSN12 INTR4/TMS LGNTO/TCK LREQI/TDO DAT0 DAT1 DVSSN11 DAT2 DVDD2 DAT3 DAT4 DAT5 DVDDO4 DAT6 DVSSN10 DAT7 DAT8 DAT9 DAT10 DAT11 DVSSN9 DAT12 NC
NC RDYRTN LRDY W/R ADS M/IO BE3 D/C RESET BE2 DVSSN5 BE1 BE0 WBACK DAT31 DAT30 DAT29 DAT28 DVSSN6 DAT27 DAT26 DAT25 DAT24 DAT23 DVDDO3 DAT22 DVSSN7 DAT21 DVSS2 DAT20 DAT19 DAT18 DAT17 DVSSN8 DAT16 DAT15 DAT14 DAT13 NC NC
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
18219-3
AM79C965A
9
PIN DESIGNATIONS: VESA VL-BUS MODE Listed by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC LED2/SRDCLK DVSSN1 ADR17 ADR16 ADR15 ADR14 DVDDO1 ADR13 ADR12 DVSSN2 ADR11 ADR10 ADR9 ADR8 ADR7 DVSSN3 ADR6 ADR5 DVSSPAD ADR4 ADR3 DVSSN4 ADR2 LBS16 DVDD1 LEADS DVSSCLK LCLK DVDDCLK VLBEN BLAST LGNT BRDY DVDDO2 LREQ DVSS1 LDEV NC NC Name Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 NC RDYRTN LRDY W/R ADS M/IO BE3 D/C RESET BE2 DVSSN5 BE1 BE0 WBACK DAT31 DAT30 DAT29 DAT28 DVSSN6 DAT27 DAT26 DAT25 DAT24 DAT23 DVDDO3 DAT22 DVSSN7 DAT21 DVSS2 DAT20 DAT19 DAT18 DAT17 DVSSN8 DAT16 DAT15 DAT14 DAT13 NC NC Name Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 NC DAT12 DVSSN9 DAT11 DAT10 DAT9 DAT8 DAT7 DVSSN10 DAT6 DVDDO4 DAT5 DAT4 DAT3 DVDD2 DAT2 DVSSN11 DAT1 DAT0 LREQI/TDO LGNTO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 NC NC Name Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 NC NC AVSS1 DO- DO+ AVDD1 DI- DI+ CI- CI+ AVDD2 ADR31 ADR30 ADR29 DVDD3 DVSS4 ADR28 ADR27 DVSSN13 ADR26 ADR25 DVDDO5 ADR24 ADR23 ADR22 ADR21 DVSSN14 ADR20 ADR19 ADR18 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY NC Name
10
AM79C965A
PIN DESIGNATIONS: VESA VL-BUS MODE Listed by Pin Name
Name ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20 ADR21 ADR22 ADR23 ADR24 ADR25 ADR26 ADR27 ADR28 ADR29 ADR30 ADR31 ADS AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BE0 BE1 BE2 Pin No. 24 22 21 19 18 16 15 14 13 12 10 9 7 6 5 4 150 149 148 146 145 144 143 141 140 138 137 134 133 132 45 126 131 115 110 123 117 53 52 50 BE3 BLAST BRDY CI+ CI- D/C DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 DAT14 DAT15 DAT16 DAT17 DAT18 DAT19 DAT20 DAT21 DAT22 DAT23 DAT24 DAT25 DAT26 DAT27 DAT28 DAT29 DAT30 DAT31 DI+ DI- Name Pin No. 47 32 34 130 129 48 99 98 96 94 93 92 90 88 87 86 85 84 82 78 77 76 75 73 72 71 70 68 66 64 63 62 61 60 58 57 56 55 128 127 DO+ DO- DVDD1 DVDD2 DVDD3 DVDDCLK DVDDO1 DVDDO2 DVDDO3 DVDDO4 DVDDO5 DVSS1 DVSS2 DVSS3 DVSS4 DVSSCLK DVSSN1 DVSSN2 DVSSN3 DVSSN4 DVSSN5 DVSSN6 DVSSN7 DVSSN8 DVSSN9 DVSSN10 DVSSN11 DVSSN12 DVSSN13 DVSSN14 DVSSN15 DVSSPAD EECS EEDI/LNKST EEDO/LEDPRE3/SRD EESK/LED1/SFBD INTR1 INTR2/EAR INTR3/TDI INTR4/TMS Name Pin No. 125 124 26 95 135 30 8 35 65 91 142 37 69 107 136 28 3 11 17 23 51 59 67 74 83 89 97 103 139 147 158 20 157 154 152 155 151 105 104 102 Name JTAGSEL LB/VESA LBS16 LCLK LDEV LEADS LED2/SRDCLK LGNT LGNTO/TCK LRDY LREQ LREQI/TDO M/IO NC NC NC NC NC NC NC NC NC NC NC NC RDYRTN RESET RXD+ RXD- SHFBUSY SLEEP TXD+ TXD- TXP+ TXP- VLBEN W/R WBACK XTAL1 XTAL2 Pin No. 106 153 25 29 38 27 2 33 101 43 36 100 46 1 39 40 41 79 80 81 119 120 121 122 160 42 49 109 108 159 156 114 112 113 111 31 44 54 116 118
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PIN DESIGNATIONS: VESA VL-BUS MODE Listed by Group
Pin Name VESA VL-Bus Interface ADR2-ADR31 ADS BE0-BE3 BLAST BRDY D/C DAT0-DAT31 INTR1 INTR2 INTR3 INTR4 JTAGSEL LB/VESA LBS16 LCLK LDEV LEADS LGNT LGNTO LRDY LREQ LREQI M/IO RDYRTN RESET VLBEN W/R WBACK Board Interface EECS EEDI/LNKST EEDO/LEDPRE3 EESK/LED1 LED2 SHFBUSY SLEEP XTAL1 XTAL2 Microwire Serial EEPROM Chip Select Microwire Serial EEPROM Data In/Link Status Microwire Address EEPROM Data Out/LED3 predriver Microwire Serial EEPROM Clock/LED1 LED Output Number 2 Shift Busy (for external EEPROM-programmable logic) Sleep Mode Crystal Input Crystal Output O O I/O O O O I I O O8 LED LED LED LED O8 1 1 1 1 1 1 1 1 1 Address Bus Address Status Byte Enable Burst Last Burst Ready Data/Control Select Data Bus Interrupt Number 1 Interrupt Number 2 Interrupt Number 3 Interrupt Number 4 JTAG Select Local Bus/VESA VL-Bus Select pin Local Bus Size 16 Local Clock Local Device Local External Address Strobe Local Bus Grant Local Grant Out Local Ready Local Bus Request Local Bus Request In Memory/I/O Select Ready Return Reset Burst Enable Write/Read Select Write Back IO I/O I/O O I/O I/O I/O O I/O I/O I/O I I I I O O I I/O O O I/O I/O I I I I/O I TS TS TS O8 TS TS O4 TS TS TS TS TS TS TS TS TS TS TS TS 30 1 4 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Function Type Driver No. of Pins
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PIN DESIGNATIONS: VESA VL-BUS MODE (continued) Listed by Group
Pin Name Attachment Unit Interface (AUI) CI+/CI- DI+/DI- DO+/DO- AUI Collision Differential Pair AUI Data In Differential Pair AUI Data Out Differential Pair I I O DO 2 2 2 Pin Function Type Driver No. of Pins
Twisted-Pair Transceiver Interface (10BASE-T) RXD+/RXD- TXD+/TXD- TXP+/TXP- LNKST/EEDI Receive Differential Pair Transmit Differential Pair Transmit Predistortion Differential Pair Link Status/Microwire Serial EEPROM Data In I O O O TDO TPO LED 2 2 2 1
IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select I/O I/O I/O I/O TS TS TS TS 1 1 1 1
External Address Detection Interface (EADI) EAR SRD SRDCLK SFBD Power Supplies AVDD AVSS DVDD DVDDCLK DVDDO DVSS DVSSCLK DVSSN DVSSPAD Analog Power Analog Ground Digital Power Digital Power Clock I/O Buffer Digital Power Digital Ground Digital Ground Clock I/O Buffer Digital Ground Digital Ground Pad P P P P P P P P P 4 2 3 1 5 4 1 15 1 External Address Reject Low Serial Receive Data Serial Receive Data Clock Start Frame--Byte Delimiter I/O I/O I/O O TS TS TS LED 1 1 1 1
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PIN DESIGNATIONS: VESA VL-BUS MODE Driver Type
Table 1. Output Drive Type Name TS O8 O4 OD LED Type Tri-State Totem Pole Totem Pole Open Drain LED IOL (mA) 8 8 4 8 12 -0.4 IOH (mA) -0.4 -0.4 -0.4 pF 50 50 50 50 50 Table 2. Pins with Pullup Signal TDI TMS TCK Pullups 10 k 10 k 10 k
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PIN DESCRIPTION: VESA VL-BUS MODE Configuration Pins JTAGSEL
JTAG Function Select Input The value of this pin will asynchronously select between JTAG Mode and Multi-Interrupt Mode. The value of this pin will asynchronously affect the function of the JTAG-INTR-Daisy chain arbitration pins, regardless of the state of the RESET pin and regardless of the state of the LCLK pin. If the value is a "1", then the PCnet-32 controller will be programmed for JTAG mode. If the value is a "0", then the PCnet-32 controller will be programmed for Multi-Interrupt Mode. When programmed for JTAG mode, four pins of the PCnet-32 controller will be configured as a JTAG (IEEE 1149.1) Test Access Port. When programmed for MultiInterrupt Mode, two of the JTAG pins will become interrupts and two JTAG pins will be used for daisy chain arbitration support. Table 3 below outlines the pin changes that will occur by programming the JTAGSEL pin.
Table 3. JTAG Pin Changes Pin LGNT0/TCK LGNT1/TDO LGNT2/TDI LGNT3/TMS JTAGSEL=1 JTAG Mode TCK TDO TDI TMS JTAGSEL=0 Multi-Interrupt Mode
Note that the setting of LB/VESA determines the f u n c t i o n a l i t y o f t h e fo l l owi n g p i n s ( n a m e s i n parentheses are pins in 486 local bus mode): VLBEN (Am486), RESET (RESET), LBS16 (AHOLD), LREQ (HOLD), LGNT (HLDA), LREQI (HOLDI) and LGNTO (HLDAO).
VLBEN
Burst Enable Input This pin is used to determine whether or not bursting is supported by the PCnet-32 device in VESA VL-Bus mode. The VLBEN pin is sampled at every rising edge of LCLK while the RESET pin is asserted. In VESA-VL mode (the LB/VESA pin is tied to VSS), if the sampled value of VLBEN is low, then the BREADE and BWRITE bits in BCR18 will be forced low, and the PCnet-32 controller will never attempt to perform linear burst reads or writes. If the sampled value of VLBEN is high, linear burst accesses are permitted, consistent with the values programmed into BREADE and BWRITE. Because of byte-duplication conventions within a 32-bit Am386 system, the PCnet-32 controller will always produce the correct bytes in the correct byte lanes in accordance with the Am386DX data sheet. This byte duplication will automatically occur, regardless of the operating mode selected by the LB/VESA pin. The VLBEN pin may be tied directly to VDD or VSS. A series resistor may be used but is not necessary. The VLBEN pin need only be valid when the RESET pin is active (regardless of the connection of the LB/ VESA pin) and may be tied to ID(3) in a VESA VL-Bus version 1.0 system, or to the logical AND of ID(4), ID(3), ID(1), and ID(0) in a VESA-VL-Bus version 1.1 or 2.0 system.
Note: This pin needs to be tied low when the LB/VESA pin has been tied to VDD. See the pin description for the Am486 pin in the Local Bus Mode section.
LGNTO LREQI
INTR3 INTR4
The JTAGSEL pin may be tied directly to VDD or VSS. A series resistor may be used but is not necessary.
LB/VESA
Local Bus/VESA VL-Bus Select Input The value of this pin will asynchronously determine the operating mode of the PCnet-32 controller, regardless of the state of the RESET pin and regardless of the state of the LCLK pin. If the LB/VESA pin is a tied to VDD, then the PCnet-32 controller will be programmed for Local Bus Mode. If the LB/VESA pin is tied to VSS, then the PCnet-32 controller will be programmed for VESA-VL Bus Mode.
Configuration Pin Settings Summary
Table 4 shows the possible pin configurations that may be invoked with the PCnet-32 controller configuration pins.
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Table 4. Configuration Pin Settings LB/VESA 0 0 1 1 1 VLBEN X* X* 0 0 1 JTAGSEL 0 1 0 1 X Mode Selected VL Bus mode with 4 interrupts and daisy chain arbitration VL Bus mode with 2 interrupts and JTAG VL Bus mode with 4 interrupts and daisy chain arbitration VL Bus mode with 2 interrupts and JTAG Reserved
*X = Don't care
Pin Connections to VDD or VSS
Several pins may be connected to V DD or V SS for various application options. Some pins are required to be connected to V DD or V SS in order to set the controller into a particular mode of operation, while other pins might be connected to VDD or VSS if that pin's function is not implemented in a specific application. Table 5 shows which pins require a connection to V DD or V SS , and which pins may optionally be connected to VDD or VSS because the application does not support that pin's function. The table also shows whether or not the connections need to be resistive.
ADS will be driven LOW when the PCnet-32 controller performs a bus master access on the local bus.
BE0-BE3
Byte Enable Input/Output These signals indicate which bytes on the data bus are active during read and write cycles. When BE3 is active, the byte on DAT31-DAT24 is valid. BE2-BE0 active indicate valid data on pins DAT23-DAT16, DAT15- DAT8, DAT7-DAT0, respectively. The byte enable signals are outputs for bus master and inputs for bus slave operations.
BLAST
Burst Last Output When the BLAST signal is asserted, then the next time that BRDY or RDYRTN is asserted, the burst cycle is complete.
VESA VL-Bus Interface ADR2-ADR31
Address Bus Input/Output Address information which is stable during a bus operation, regardless of the source. When the PCnet-32 controller is Current Master, A2-A31 will be driven. When the PCnet-32 controller is not Current Master, the A2-A31 lines are continuously monitored to determine if an address match exists for I/O slave transfers.
BRDY
Burst Ready Input/Output BRDY functions as an input to the PCnet-32 controller during bus master cycles. When BRDY is asserted during a master cycle, it indicates to the PCnet-32 controller that the target device is accepting burst transfers. It also serves the same function as RDYRTN does for non-burst accesses. That is, it indicates that the target device has accepted the data on a master write cycle, or that the target device has presented valid data onto the bus during master read cycles.
ADS
Address Status Input/Output When driven LOW, this signal indicates that a valid bus cycle definition and address are available on the M/IO, D/C, W/R and A2-A31 pins of the local bus interface. At that time, the PCnet-32 controller will examine the combination of M/IO, D/C, W/R, and the A2-A31 pins to determine if the current access is directed toward the PCnet-32 controller.
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Table 5. Pin Connections to Power/Ground
Pin Name LED2/SRDCLK LBS16 VLBEN WBACK LREQI/TDO JTAGSEL EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1SFBD
Pin No 2 25 31 54 100 106 152 153 154 155
Supply Strapping Required Optional Required Optional Optional Required Optional Required Optional Required
Resistive Connection to Supply Required Required Optional Required Required Optional Required Optional Required Required
Recommended Resistor Size 324 in series with LED, or 10 K without LED 10 K NA 10 K 10 K NA 10 K NA 324 in series with LED, or 10 K without LED 324 in series with LED, or 10 K without LED 10 K 10 K
SLEEP All Other Pins
156 --
Optional Optional
Required Required
If BRDY and RDYRTN are sampled active in the same cycle, then RDYRTN takes precedence, causing the next transfer cycle to begin with a T1 cycle. BRDY functions as an output during PCnet-32 controller slave cycles and is always driven inactive (HIGH). BRDY is floated if the PCnet-32 controller is not being accessed as the current slave device on the local bus.
DAT31-DAT0 is latched by the PCnet-32 controller when performing bus master reads and slave write operations. The PCnet-32 controller will always follow Am386DX byte lane conventions. This means that for word and byte accesses in which PCnet-32 controller drives the data bus (i.e. master write operations and slave read operations), the PCnet-32 controller will produce duplicates of the active bytes on the unused half of the 32bit data bus. Table 6 illustrates the cases in which duplicate bytes are created.
Table 6. Bye Duplication on Data Bus BE3-BE0 1110 1101 1011 0111 1100 1001 0011* 1000 0001 0000 DAT [31:24] Undef Undef Undef A Undef Undef D Undef D D DAT [23:16] Undef Undef A Undef Undef C C C C C DAT [15:8] Undef A Undef Copy A B B Copy D B B B DAT [7:0] A Undef Copy A Undef A Undef Copy C A Undef A
D/C
Data/Control Select Input/Output During slave accesses to the PCnet-32 controller, the D/C pin, along with M/IO and W/R, indicates the type of cycle that is being performed. PCnet-32 controller will only respond to local bus accesses in which D/C is driven HIGH by the local bus master. During PCnet-32 controller bus master accesses, the D/C pin is an output and will always be driven HIGH. D/C is floated if the PCnet-32 controller is not the current master on the local bus.
DAT0-DAT31
Data Bus Input/Output Used to transfer data to and from the PCnet-32 controller to system resources via the local bus. DAT31-DAT0 are driven by the PCnet-32 controller when performing bus master writes and slave read operations. Data on
*Note: Byte duplication does not apply during an LBS16 access, see Table 8.
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INTR1-INTR4
Interrupt Request Output An attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR,RINT, IDON, MFCO, RCVCCO, TXSTRT, or JAB. Each of these status flags has a mask bit which allows for suppression of INTR assertion. These flags have the meaning shown in Table 7.
Table 7. Status Flags
BABL MISS MERR RINT IDON MFCO Babble (CSR0, bit 14) Missed Frame (CSR0, bit 12) Memory Error (CSR0, bit 11) Receive Interrupt (CSR0, bit 10) Initialization Done (CSR0, bit 8) Missed Packet Count Overflow (CSR4, bit 9) Receive Collision Count Overflow (CSR4, bit 5) Transmit Start (CSR4, bit 3) Jabber (CSR4, bit 1)
the JTAGSEL pin. Only one interrupt pin may be used at one time. The active interrupt pin is selected by programming the interrupt select register (BCR21). The default setting of BCR121will select interrupt INTR1 as the active interrupt. Note that BCR21 is EEPROM-programmable. Inactive interrupt pins are floated. The polarity of the interrupt signal is determined by the INTLEVEL bit of BCR2. The interrupt pins may be programmed for level-sensitive or edge-sensitive operation. PCnet-32 controller interrupt pins will be floated at H_RESET and will remain floated until either the EEPROM has been successfully read, or, following an EEPROM read failure, a Software Relocatable Mode sequence has been successfully executed.
LBS16
Local Bus Size 16 Input BS16 is sampled during PCnet-32 controller bus mastering activity to determine if the target device on the VL-Bus is 32 or 16 bits in width. If the LBS16 signal is sampled active at least one clock period before the assertion of LRDY during a PCnet-32 controller bus master transfer, then the PCnet-32 controller will convert a single 32-bit transfer into two 16-bit transfers. Not all 32-bit transfers need to be split into two 16-bit transfers. Table 8 shows the sequence of transfers that will be executed for each possible 32-bit bus transfer that encounters a proper assertion of the LBS16 signal.
RCVCCO
TXSTRT JAB
Note that there are four possible interrupt pins, depending upon the mode that has been selected with
Table 8. Data Transfer Sequence from 32-Bit Wide to 16-Bit Wide Current Access BE3 1 1 1 0 1 1 0 1 0 0 BE2 1 1 0 0 1 0 0 0 0 1 BE1 1 0 0 0 0 0 0 1 1 1 BE0 0 0 0 0 1 1 1 1 1 1 BE3 NR NR 1 0 NR 1 0 NR NR NR 0 0 1 1 1 1 0 0 1 1 1 1 Next with LBS16 BE2 BE1 BE0
NR = No second access Required for these cases. During accesses in which PCnet-32 controller is acting the VL-Bus target device, the LBS16 signal will not be driven. In this case, it is expected that the VL-Bus required pull-up device will bring the LBS16 signal to an inactive level and the PCnet-32 controller will be seen by the VL-Bus master as a 32-bit peripheral.
LCLK
Local Clock Input LCLK is a 1x clock that follows the same phase as a 486-type CPU clock. LCLK is always driven by the system logic or the VL-Bus controller to all VL-Bus masters and targets. The rising edge of the clock signifies the change of CPU states, and hence, the change of PCnet-32 controller states.
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LDEV
Local Device Output LDEV is driven by the PCnet-32 controller when it recognizes an access to PCnet-32 controller I/O space. Such recognition is dependent upon a valid sampled ADS strobe plus valid M/IO, D/C and ADR31-ADR5 values.
Note that this pin changes polarity when Local Bus mode has been selected (see pin description of HLDAO 486 Local Bus Interface section).
LRDY
Local Ready Output LRDY functions as an output from the PCnet-32 controller during PCnet-32 controller slave cycles. During PCnet-32 controller slave read cycles, LRDY is asserted to indicate that valid data has been presented on the data bus. During PCnet-32 controller slave write cycles, LRDY is asserted to indicate that the data on the data bus has been internally latched. LRDY will be asserted low for one clock period when the PCnet-32 controller wishes to terminate the cycle. LRDY is then driven high for one-half of one clock period before being released. LRDY is floated if the PCnet-32 controller is not the current slave on the local bus.
LEADS
Local External Address Strobe Output During VL-Bus master write and read accesses the LEADS pin will be asserted on every T1 cycle as is specified in the VESA VL-Bus specification, regardless the settings of the GCIC bit of BCR18 and the CLL bits BCR18.
LGNT
Local Bus Grant Input When LGNT is asserted and LREQ is being asserted by the PCnet-32 controller, the PCnet-32 controller assumes ownership of the VL bus. Note that this pin changes polarity when Local Bus mode has been selected (see pin description of HLDA in 486 Local Bus Interface section).
LREQ
Local Bus Request Output LREQ is used by the PCnet-32 controller to gain control of the VL-Bus and become the active VL Bus Master. LREQ is active low. Once asserted, LREQ remains active until LGNT has become active, independent of subsequent assertion of SLEEP or setting of the STOP bit or access to the S_RESET port (offset 14h). Note that this pin changes polarity when Local Bus mode has been selected (see pin description of HOLD in 486 Local Bus Interface section).
LGNTO
Local Grant Out Output This signal is multiplexed with the TCK pin, and is available only when the Multi-Interrupt mode has been selected with the JTAGSEL pin.
An additional local bus master may daisy-chain its LGNT signal through the PCnet-32 controller LGNTO pin. The
LREQI
Local Bus Request In Input This signal is multiplexed with the TDO pin, and is available only when the Multi-Interrupt mode has been selected with the JTAGSEL pin. An additional local bus master may daisy-chain its bus hold request signal through the PCnet-32 controller LREQI pin. The PCnet-32 controller will convey the LREQI request to the arbitration logic via the PCnet-32 controller LREQ output. The second local bus master must connect its LGNT input to the LGNTO output of the PCnet-32 controller in order to complete the local bus daisy-chain arbitration control. When SLEEP is not asserted, daisy chain arbitration signals that pass through the PCnet-32 controller will experience a one-clock delay from input to output (i.e. LREQI to LREQ and LGNT to LGNTO). While SLEEP is asserted (either in snooze mode or coma mode), if the PCnet-32 controller is configured for daisy chain (LREQI and LGNTO signals have been selected with the JTAGSEL pin), then the daisy-chain signal LREQI will be passed directly to the system arbi-
PCnet-32 controller will deliver a LGNTO signal the additional local bus master whenever the PCnet-32 controller receives a LGNT from the arbitration logic, but is not simultaneously requesting the bus internally. The second local bus master must connect its LREQ output to the LREQI input of the PCnet-32 controller in order to complete the local bus daisy-chain arbitration control. When SLEEP is not asserted, daisy chain arbitration signals that pass through the PCnet-32 controller will experience a one-clock delay from input to output (i.e. LREQI to LREQ and LGNT to LGNTO). While SLEEP is asserted (either in snooze mode or coma mode), if the PCnet-32 controller is configured for daisy chain (LREQI and LGNTO signals have been selected with the JTAGSEL pin), then the system arbitration signal LGNT will be passed directly to the daisychain signal LGNTO without experiencing a one-clock delay. However, some combinatorial delay will be introduced in this path.
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tration signal LREQ without experiencing a one-clock delay. However, some combinatorial delay will be introduced in this path. Multi-Interrupt mode has been selected and the daisychain arbitration feature is not used, then the LREQI input should be tied to VDD. Note that this pin changes polarity when Local Busmode has been selected (see pin description of HOLDI in 486 Local Bus Interface section).
LRDY signal. The CPU READY signal should be connected to the PCnet-32 controller RDYRTN pin. In systems where only one READY signal is provided, then the PCnet-32 controller LRDY output may be tied the PCnet-32 controller RDYRTN input.
RESET
System Reset Input When RESET is asserted low and the LB/VESA pin has been tied to VSS, then the PCnet-32 controller performs an internal system reset of the H_RESET type (HARDWARE_ RESET). The RESET pin must be held for a minimum of 30 LCLK periods when VL mode has been selected. While in the H_RESET state, the PCnet-32 controller will float or de-assert all outputs.
M/IO
Memory I/O Select Input/Output During slave accesses to the PCnet-32 controller, the M/IO pin, along with D/C and W/R, indicates the type cycle that is being performed. PCnet-32 controller will only respond to local bus accesses in which M/IO sampled as a zero by the PCnet-32 controller. During PCnet-32 controller bus master accesses, the M/IO pin is an output and will always be driven high. M/IO is floated if the PCnet-32 controller is not the current master on the local bus.
W/R
Write/Read Select Input/Output During slave accesses to the PCnet-32 controller, the W/R pin, along with D/C and M/IO, indicates the type of cycle that is being performed. During PCnet-32 controller bus master accesses, the W/R pin is an output. W/R is floated if the PCnet-32 controller is not the current master on the local bus.
RDYRTN
Ready Return Input RDYRTN functions as an input to the PCnet-32 controller. RDYRTN is used to terminate all master accesses performed by the PCnet-32 controller, except that linear burst transfers may also be terminated with the BRDY signal. RDYRTN is used to terminate slave read accesses to PCnet-32 controller I/O space. When asser ted dur ing slave read accesses to PCnet-32 controller I/O space, RDYRTN indicates that the bus mastering device has seen the LRDY that was generated by the PCnet-32 controller and has accepted the PCnet-32 controller slave read data. Therefore, PCnet-32 controller will hold slave read data on the bus until it synchronously samples the RDYRTN input as active low. The PCnet-32 controller will not hold LRDY valid asserted during this time. The duration of the LRDY pulse generated by the PCnet-32 controller will always be a single LCLK cycle. RDYRTN is ignored during slave write accesses PCnet-32 controller I/O space. Slave write accesses PCnet-32 controller I/O space are considered terminated by the PCnet-32 controller at the end of the cycle during which the PCnet-32 controller issues an active RDY. In systems where both a LRDY and RDYRTN (or equivalent) signals are provided, then LRDY must not be tied to RDYRTN. Most systems now provide for local device ready input to the memory controller that separate from the CPU READY signal. This second READY signal is usually labeled as READYIN. This signal should be connected to the PCnet-32 controller
WBACK
Write Back Input WBACK is monitored as in input during VL-Bus Master Accesses. When PCnet-32 controller is current VL-Bus master, the PCnet-32 controller will float all appropriate bus mastering signals within 1 clock period of the assertion of WBACK. When WBACK is de-asserted, PCnet-32 controller will re-execute any accesses that were suspended due to the assertion of WBACK and then will proceed with other scheduled accesses, if any. Register access cannot be performed to the PCnet-32 device while WBACK is asserted.
Board Interface LED1
LED1 Output This pin is shared with the EESK function. When operating as LED1, the function and polarity on this pin are programmable through BCR5. The LED1 output from the PCnet-32 controller is capable of sinking the necessary 12 mA of current to drive an LED directly. The LED1 pin is also used during EEPROM Autodetection to determine whether or not an EEPROM is present at the PCnet-32 controller microwire interface. At the trailing edge of RESET, this pin is sampled to determine the value of the EEDET bit in BCR19. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to ONE. A sampled
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LOW value means that an EEPROM is not present, and EEDET will be set to ZERO. See the "EEPROM Autodetection" section for more details. If no LED circuit is to be attached to this pin, then a pullup or pull-down resistor must be attached instead, in order to resolve the EEDET setting.
LNKST
Link Status Output This pin provides 12 mA for driving an LED. It indicates an active link connection on the 10BASE-T interface. The function and polarity are programmable through BCR4. Note that this pin is multiplexed with the EEDI function. This pin remains active in snooze mode.
LED2
LED2 Output This pin is shared with the SRDCLK function. When operating as LED2, the function and polarity on this pin are programmable through BCR6. The LED2 output from the PCnet-32 controller is capable of sinking the necessary 12 mA of current to drive an LED directly. This pin also selects address width for Software Relocatable Mode. When this pin is HIGH during Software Relocatable Mode, then the device will be programmed to use 32 bits of addressing while snooping accesses on the bus during Software Relocatable Mode. When this pin is LOW during Software Relocatable Mode, then the device will be programmed to use 24 bits of addressing while snooping accesses on the bus during Software Relocatable Mode. The upper 8 bits of address will be assumed to match during the snooping operation when LED2 is LOW. The 24-bit addressing mode is intended for use in systems that employ the GPSI signals. For more information on the GPSI function see section General Purpose Serial Interface. If no LED circuit is to be attached to this pin, then a pull up or pull down resistor must be attached instead, in order to resolve the Software Relocatable Mode address width setting.
SHFBUSY
Shift Busy Output The function of the SHFBUSY signal is to indicate when the last byte of the EEPROM contents has been shifted out of the EEPROM on the EEDO signal line. This information is useful for external EEPROMprogrammable registers that do not use the microwire protocol, as is described herein: When the PCnet-32 controller is performing a serial read of the EEPROM through the microwire interface, the SHFBUSY signal will be driven HIGH. SHFBUSY can serve as a serial shift enable to allow the EEPROM data to be serially shifted into an external device or series of devices. The SHFBUSY signal will remain actively driven HIGH until the end of the EEPROM read operation. If the EEPROM checksum was verified, then the SHFBUSY signal will be driven LOW at the end of the EEPROM read operation. If the EEPROM checksum verification failed, then the SHFBUSY signal will remain HIGH. This function effectively demarcates the end of a successful EEPROM read operation and therefore is useful as a programmable-logic low-active output enable signal. For more details on external EEPROMprogrammable registers, see the EEPROM Microwire Access section under Hardware Access. This pin can be controlled by the host system by writing to BCR19, bit 3 (EBUSY).
LEDPRE3
LEDPRE3 Output This pin is shared with the EEDO function. When operating as LEDPRE3, the function and polarity on this pin are programmable through BCR7. This signal is labeled as LED "PRE" 3 because of the multifunction nature of this pin. If an LED circuit were directly attached to this pin, it would create an IOL requirement that could not be met by the serial EEPROM that would also be attached to this pin. Therefore, if this pin is to be used as an additional LED output while an EEPROM is used in the system, then buffering is required between the LEDPRE3 pin and the LED circuit. If no EEPROM is included in the system design, then the LEDPRE3 signal may be directly connected to an LED without buffering. The LEDPRE3 output from the PCnet-32 controller is capable of sinking the necessary 12 mA of current to drive an LED in this case. For more details regarding LED connection, see the section on LEDs.
SLEEP
Sleep Input When SLEEP input is asserted (active LOW), the PCnet-32 controller performs an internal system reset of the S_RESET type and then proceeds into a power savings mode. (The reset operation caused by SLEEP assertion will not affect BCR registers.) All outputs will be placed in their normal S_RESET condition. During sleep mode, all PCnet-32 controller inputs will be ignored except for the SLEEP pin itself. De-assertion of SLEEP results in wake-up. The system must refrain from starting the network operations of the PCnet-32 controller for 0.5 seconds following the de-assertion of the SLEEP signal in order to allow internal analog circuits to stabilize. Both LCLK and XTAL1 inputs must have valid clock signals present in order for the SLEEP command to take effect.
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If SLEEP is asserted while LREQ is asserted, then the PCnet-32 controller will perform an internal system S_RESET and then wait for the assertion of LGNT. When LGNT is asserted, the LREQ signal will be deasserted and then the PCnet-32 controller will proceed to the power savings mode. Note that the internal system S_RESET will not cause the LREQ signal to be de-asserted. The SLEEP pin should not be asserted during power supply ramp-up. If it is desired that SLEEP be asserted at power-up time, then the system must delay the assertion of SLEEP until three LCLK cycles after the completion of a valid pin RESET operation.
a serial shift enable to allow the EEPROM data to be serially shifted into an external device or series of devices. This same signal can be used to gate the output of the programmed logic to avoid the problem of releasing intermediate values to the rest of the system board logic. The EESK signal can serve as the clock, and EEDO will serve as the input data stream to the programmable shift register.
EEDO
EEPROM Data Out Input The EEDO signal is used to access the external ISO 8802-3 (IEEE/ANSI 802.3) address PROM. This pin is designed to directly interface to a serial EEPROM that uses the microwire interface protocol. EEDO is connected to the microwire EEPROM's Data Output pin. It is controlled by the EEPROM during reads. It may be read by the host system by reading BCR19, bit 0. EEDO can be used during programming of external EEPROM-programmable registers that do not use the microwire protocol as follows: When the PCnet-32 controller is performing a serial read of the IEEE Address EEPROM through the microwire interface, the SHFBUSY signal will serve as a serial shift enable to allow the EEPROM data to be serially shifted into an external device or series of devices. This same signal can be used to gate the output of the programmed logic to avoid the problem of releasing intermediate values to the rest of the system board logic. The EESK signal can serve as the clock, and EEDO will serve as the input data stream to the programmable shift register.
XTAL1-XTAL2
Crystal Oscillator Inputs Input/Output The crystal frequency determines the network data rate. The PCnet-32 controller supports the use of quar tz crystals to generate a 20 MHz frequency compatible with the ISO 8802-3 (IEEE/ANSI 802.3) network frequency tolerance and jitter specifications. See the section External Crystal Characteristics (in section Manchester Encoder/Decoder) for more detail. The network data rate is one-half of the crystal frequency. XTAL1 may alternatively be driven using an external CMOS level source, in which case XTAL2 must be left unconnected. Note that when the PCnet-32 controller is in coma mode, there is an internal 22 KW resistor from XTAL1 to ground. If an external source drives XTAL1, some power will be consumed driving this resistor. If XTAL1 is driven LOW at this time power consumption will be minimized. In this case, XTAL1 must remain active for at least 30 cycles after the assertion of SLEEP and de-assertion of LREQ.
EECS
EEPROM Chip Select Output
Microwire EEPROM Interface EESK
EEPROM Serial Clock Output The EESK signal is used to access the external ISO 8802-3 (IEEE/ANSI 802.3) address PROM. This pin is designed to directly interface to a serial EEPROM that uses the microwire interface protocol. EESK is connected to the microwire EEPROM's Clock pin. It is controlled by either the PCnet-32 controller directly during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 1. EESK can be used d u r i n g p r o g r a m m i n g o f ex t e r n a l E E P R O M programmable registers that do not use the microwire protocol as follows: When the PCnet-32 controller is performing a serial read of the IEEE Address EEPROM through the microwire interface, the SHFBUSY signal will serve as
The function of the EECS signal is to indicate to the microwire EEPROM device that it is being accessed. The EECS signal is active high. It is controlled by either the PCnet-32 controller during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 2.
EEDI
EEPROM Data In Output The EEDI signal is used to access the external ISO 8802-3 (IEEE/ANSI 802.3) address PROM. EEDI functions as an output. This pin is designed to directly interface to a serial EEPROM that uses the microwire interface protocol. EEDI is connected to the microwire EEPROM's Data Input pin. It is controlled by either the PCnet-32 controller during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 0.
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AM79C965A
Attachment Unit Interface CI
Collision In Input A differential input pair signaling the PCnet-32 controller that a collision has been detected on the network media, indicated by the CI inputs being driven with a 10 MHz pattern of sufficient amplitude and pulse width to meet ISO 8802-3 (IEEE/ANSI 802.3) standards. Operates at pseudo ECL levels.
SFBD
Start Frame-Byte Delimiter Output Start Frame-Byte Delimiter Enable. EADI output signal. An initial rising edge on this signal indicates that a start of frame delimiter has been detected. The serial bit stream will follow on the SRD signal, commencing with the destination address field. SFBD will go high for 4 bit times (400 ns) after detecting the second "1" in the SFD (Start of Frame Delimiter) of a received frame. SFBD will subsequently toggle every 400 ns (1.25 MHz frequency) with each rising edge indicating the first bit of each subsequent byte of the received serial bit s t r e a m . S F B D w i l l b e i n a c t i ve d u r i n g f r a m e transmission. Note that this pin is multiplexed with the LED1 pin.
DI
Data In Input A differential input pair to the PCnet-32 controller carrying Manchester encoded data from the network. Operates at pseudo ECL levels.
DO
Data Out Output A differential output pair from the PCnet-32 controller for transmitting Manchester encoded data to the network. Operates at pseudo ECL levels.
SRD
Serial Receive Data Output An EADI output signal. SRD is the decoded NRZ data from the network. This signal can be used for external address detection. Note that when the 10BASE-T port is selected, transitions on SRD will only occur during receive activity. When the AUI por t is selected, transitions on SRD will occur during both transmit and receive activity. Note that this pin is multiplexed with the LEDPRE3 pin.
Twisted Pair Interface RXD
10BASE-T Receive Data 10BASE-T port differential receivers. Input
TXD
10BASE-T Transmit Data 10BASE-T port differential drivers. Output
SRDCLK
Serial Receive Data Clock Output An EADI output signal. Serial Receive Data is synchronous with reference to SRDCLK. Note that when the 10BASE-T port is selected, transitions on SRDCLK will only occur during receive activity. When the AUI port is selected, transitions on SRDCLK will occur during both transmit and receive activity. Note that this pin is multiplexed with the LED2 pin.
TXP
10BASE-T Pre-distortion Control Output These outputs provide transmit predistortion control in conjunction with the 10BASE-T port differential drivers.
External Address Detection Interface
The EADI interface is enabled through bit 3 of BCR2 (EADISEL).
General Purpose Serial Interface
The GPSI interface is selected through the PORTSEL bits of the Mode register (CSR15) and enabled through the TSTSHDW[1] bit (BCR18) or the CORETEST bit (CSR124). Note that when GPSI test mode is invoked, slave address decoding must be restricted to the lower 24 bits of the address bus by setting the IOAW24 bit in BCR2 and by pulling LED2 LOW during Software Relocatable Mode. The upper 8 bits of the address bus will always be considered matched when examining incoming I/O addresses. During master accesses while in GPSI mode, the PCnet-32 controller will not drive the upper 8 bits of the address bus with address information. See the GPSI section for more detail.
EAR
External Address Reject Low Input An EADI input signal. The incoming frame will be checked against the internally active address detection mechanisms and the result of this check will be OR'd with the value on the EAR pin. The EAR pin is defined as REJECT. See the EADI section for details regarding the function and timing of this signal. Note that this pin is multiplexed with the INTR2 pin.
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TXDAT
Transmit Data Input/Output TXDAT is an output, providing the serial bit stream for transmission, including preamble, SFD data and FCS field, if applicable. Note that the TxDAT pin is multiplexed with the A31 pin.
Note that the RXDAT pin is multiplexed with the A25 pin.
IEEE 1149.1 Test Access Port Interface TCK
Test Clock Input The clock input for the boundary scan test mode operation. TCK can operate up to 10 MHz. If left unconnected, this pin has a default value of HIGH.
TXEN
Transmit Enable Input/Output TXEN is an output, providing an enable signal for transmission. Data on the TXDAT pin is not valid unless the TXEN signal is HIGH. Note that the TXEN pin is multiplexed with the A30 pin.
TDI
Test Data Input Input The test data input path to the PCnet-32 controller. If left unconnected, this pin has a default value of HIGH.
STDCLK
Serial Transmit Data Clock Input STDCLK is an input, providing a clock signal for MAC activity, both transmit and receive. Rising edges of the STDCLK can be used to validate TXDAT output data. The STDCLK pin is multiplexed with the A29 pin. Note that this signal must meet the frequency stability requirement of the ISO 8802-3 (IEEE/ANSI 802.3) specification for the crystal.
TDO
Test Data Output Output The test data output path from the PCnet-32 controller. TDO is floated when the JTAG port is inactive.
TMS
Test Mode Select Input A serial input bit stream is used to define the specific boundary scan test to be executed. If left unconnected, this pin has a default value of HIGH.
CLSN
Collision Input/Output CLSN is an input, indicating to the core logic that a collision has occurred on the network. Note that the CLSN pin is multiplexed with the A28 pin.
Power Supply Pins AVDD
Analog Power (4 Pins) Power There are four analog +5 Volt supply pins. Special attention should be paid to the printed circuit board layout to avoid excessive noise on these lines. Refer to Appendix B and the PCnet Family Technical Manual (PID# 18216A) for details.
RXCRS
Receive Carrier Sense Input/Output RXCRS is an input. When this signal is HIGH, it indicates to the core logic that the data on the RXDAT input pin is valid. Note that the RXCRS pin is multiplexed with the A27 pin.
AVSS
Analog Ground (2 Pins) Power There are two analog ground pins. Special attention should be paid to the printed circuit board layout to avoid excessive noise on these lines. Refer to Appendix B and the PCnet Family Technical Manual for details.
SRDCLK
Serial Receive Data Clock Input/Output SRDCLK is an input. Rising edges of the SRDCLK signal are used to sample the data on the RXDAT input whenever the RXCRS input is HIGH. Note that the SRDCLK pin is multiplexed with the A26 pin.
DVDD
Digital Power (3 Pins) Power There are 3 digital power supply pins (DVDD1, DVDD 2, and DVDD3) used by the internal digital circuitry.
RXDAT
Receive Data Input/Output RXDAT is an input. Rising edges of the SRDCLK signal are used to sample the data on the RXDAT input whenever the RXCRS input is HIGH.
DVDDCLK
Digital Power Clock (1 Pin) Power This pin is used to supply power to the clock buffering circuitry.
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AM79C965A
DVDDO
I/O Buffer Digital Power (5 Pins) used by Input/Output buffer drivers. Power
There are 5 digital power supply pins (DVDDO1-DVDDO5)
DVSSCLK
Digital Ground Clock (1 Pin) Ground This pin is used to supply a ground to the clock buffering circuitry.
DVSS
Digital Ground (4 Pins)
by the internal digital circuitry.
DVSSN
Ground I/O Buffer Digital Ground (15 Pins)
by the Input/Output buffer drivers.
Ground
There are 4 digital ground pins (DVSS1-DVSS4) used
These 15 ground pins (DVSSN1-DVSSN15) are used
DVSSPAD
Digital Ground Pad (1 Pin) Ground This pin is used by the Input/Output logic circuits.
AM79C965A
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VESA VL-BUS / LOCAL BUS PIN CROSS-REFERENCE Listed by Pin Number
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VESA VL-Bus Mode Pin Name NC LED2/SRDCLK DVSSN1 ADR17 ADR16 ADR15 ADR14 DVDDO1 ADR13 ADR12 DVSSN2 ADR11 ADR10 ADR9 ADR8 ADR7 DVSSN3 ADR6 ADR5 DVSSPAD ADR4 ADR3 DVSSN4 ADR2 LBS16 DVDD1 LEADS DVSSCLK LCLK DVDDCLK VLBEN BLAST LGNT BRDY DVDDO2 LREQ DVSS1 LDEV NC NC NC LED2/SRDCLK DVSSN1 A17 A16 A15 A14 DVDDO1 A13 A12 DVSSN2 A11 A10 A9 A8 A7 DVSSN3 A6 A5 DVSSPAD A4 A3 DVSSN4 A2 AHOLD DVDD1 EADS DVSSCLK BCLK DVDDCLK Am486 BLAST HLDA BRDY DVDDO2 HOLD DVSS1 LDEV NC NC Local Bus Mode Pin Name Pin # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VESA VL-Bus Mode Pin Name NC RDYRTN LRDY W/R ADS M/IO BE3 D/C RESET BE2 DVSSN5 BE1 BE0 WBACK DAT31 DAT30 DAT29 DAT28 DVSSN6 DAT27 DAT26 DAT25 DAT24 DAT23 DVDDO3 DAT22 DVSSN7 DAT21 DVSS2 DAT20 DAT19 DAT18 DAT17 DVSSN8 DAT16 DAT15 DAT14 DAT13 NC NC NC RDYRTN RDY W/R ADS M/IO BE3 D/C RESET BE2 DVSSN5 BE1 BE0 BOFF D31 D30 D29 D28 DVSSN6 D27 D26 D25 D24 D23 DVDDO3 D22 DVSSN7 D21 DVSS2 D20 D19 D18 D17 DVSSN8 D16 D15 D14 D13 NC NC Local Bus Mode Pin Name
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AM79C965A
VESA VL-BUL / LOCAL BUS PIN CROSS-REFERENCE (continued) Listed by Pin Number
Pin # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VESA VL-Bus Mode Pin Name NC DAT12 DVSSN9 DAT11 DAT10 DAT9 DAT8 DAT7 DVSSN10 DAT6 DVDDO4 DAT5 DAT4 DAT3 DVDD2 DAT2 DVSSN11 DAT1 DAT0 LREQI/TDO LGNTO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXDRXD+ AVDD4 TXPTXDTXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 NC NC NC D12 DVSSN9 D11 D10 D9 D8 D7 DVSSN10 D6 DVDDO4 D5 D4 D3 DVDD2 D2 DVSSN11 D1 D0 HOLDI/TDO HLDAO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXDRXD+ AVDD4 TXPTXDTXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 NC NC Local Bus Mode Pin Name Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 VESA VL-Bus Mode Pin Name NC NC AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 ADR31 ADR30 ADR29 DVDD3 DVSS4 ADR28 ADR27 DVSSN13 ADR26 ADR25 DVDDO5 ADR24 ADR23 ADR22 ADR21 DVSSN14 ADR20 ADR19 ADR18 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY NC NC NC AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 A31 A30 A29 DVDD3 DVSS4 A28 A27 DVSSN13 A26 A25 DVDDO5 A24 A23 A22 A21 DVSSN14 A20 A19 A18 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY NC Local Bus Mode Pin Name
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BLOCK DIAGRAM: 486 LOCAL BUS MODE
BCLK BE0 BE3 ADS BRDY BOFF BLAST RDY RDYRTN M/IO D/C W/R INTR1 INTR4 HOLD HOLDI HLDA HLDAO SLEEP LDEV EADS AHOLD RESET A2 A31 D0 D31 Am486 LB/VESA
Rcv FIFO
802.3 MAC Core CI+/ DI+/ XTAL1 XTAL2 DO+/ RXD+/ 10BASE-T MAU TXD+/ TXP+/ LNKST
Manchester Encoder/ Decoder (PLS) and AUI Port 486 Local Bus Interface Unit Xmt FIFO
FIFO Control
Microwire, LED, and JTAG Control Buffer Management Unit
EEDI EECS EESK EEDO SHFBUSY LED1-LED3 TCK TDI TMS TDO
18219-2
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AM79C965A
CONNECTION DIAGRAM: 486 LOCAL BUS MODE
NC SHFBUSY DVSSN15 EECS SLEEP EESK/LED1/SFBD EEDI/LNKST LB/VESA EEDO/LEDPRE3/SRD INTR1 A18 A19 A20 DVSSN14 A21 A22 A23 A24 DVDDO5 A25 A26 DVSSN13 A27 A28 DVSS4 DVDD3 A29 A30 A31 AVDD2 CI+ CI- DI+ DI- AVDD1 DO+ DO- AVSS1 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
NC RDYRTN RDY W/R ADS M/IO BE3 D/C RESET BE2 DVSSN5 BE1 BE0 BOFF D31 D30 D29 D28 DVSSN6 D27 D26 D25 D24 D23 DVDD03 D22 DVSSN7 D21 DVSS2 D20 D19 D18 D17 DVSSN8 D16 D15 D14 D13 NC NC
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
NC LED2/SRDCLK DVSSN1 A17 A16 A15 A14 DVDD01 A13 A12 DVSSN2 A11 A10 A9 A8 A7 DVSSN3 A6 A5 DVSSPAD A4 A3 DVSSN4 A2 AHOLD DVDD1 EADS DVSSCLK BCLK DVDDCLK Am486 BLAST HLDA BRDY DVDDO2 HOLD DVSS1 LDEV NC NC
Am79C971
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC NC XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXD- TXP- AVDD4 RXD+ RXD- DVSS3 JTAGSEL INTR2/EAR INTR3/TDI DVSSN12 INTR4/TMS HLDAO/TCK HOLDI/TDO D0 D1 DVSSN11 D2 DVDD2 D3 D4 D5 DVDDO4 D6 DVSSN10 D7 D8 D9 D10 D11 DVSSN9 D12 NC
18219-4
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PIN DESIGNATIONS: 486 LOCAL BUS MODE Listed by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC LED2/SRDCLK DVSSN1 A17 A16 A15 A14 DVDDO1 A13 A12 DVSSN2 A11 A10 A9 A8 A7 DVSSN3 A6 A5 DVSSPAD A4 A3 DVSSN4 A2 AHOLD DVDD1 EADS DVSSCLK BCLK DVDDCLK Am486 BLAST HLDA BRDY DVDDO2 HOLD DVSS1 LDEV NC NC Name Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 NC RDYRTN RDY W/R ADS M/IO BE3 D/C RESET BE2 DVSSN5 BE1 BE0 BOFF D31 D30 D29 D28 DVSSN6 D27 D26 D25 D24 D23 DVDDO3 D22 DVSSN7 D21 DVSS2 D20 D19 D18 D17 DVSSN8 D16 D15 D14 D13 NC NC Name Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 NC D12 DVSSN9 D11 D10 D9 D8 D7 DVSSN10 D6 DVDDO4 D5 D4 D3 DVDD2 D2 DVSSN11 D1 D0 HOLDI/TDO HLDAO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 NC NC Name Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 NC NC AVSS1 DO- DO+ AVDD1 DI- DI+ CI- CI+ AVDD2 A31 A30 A29 DVDD3 DVSS4 A28 A27 DVSSN13 A26 A25 DVDDO5 A24 A23 A22 A21 DVSSN14 A20 A19 A18 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY NC Name
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AM79C965A
PIN DESIGNATIONS: 486 LOCAL BUS MODE Listed by Pin Name
Name A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ADS AHOLD Am486 AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BCLK Pin No. 24 22 21 19 18 16 15 14 13 12 10 9 7 6 5 4 150 149 148 146 145 144 143 141 140 138 137 134 133 132 45 25 31 126 131 115 110 123 117 29 Name BE0 BE1 BE2 BE3 BLAST BOFF BRDY CI+ CI- D/C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 Pin No. 53 52 50 47 32 54 34 130 129 48 99 98 96 94 93 92 90 88 87 86 85 84 82 78 77 76 75 73 72 71 70 68 66 64 63 62 61 60 58 57 D30 D31 DI+ DI- DO+ DO- DVDD1 DVDD2 DVDD3 DVDDCLK DVDDO1 DVDDO2 DVDDO3 DVDDO4 DVDDO5 DVSS1 DVSS2 DVSS3 DVSS4 DVSSCLK DVSSN1 DVSSN2 DVSSN3 DVSSN4 DVSSN5 DVSSN6 DVSSN7 DVSSN8 DVSSN9 DVSSN10 DVSSN11 DVSSN12 DVSSN13 DVSSN14 DVSSN15 DVSSPAD EADS EECS EEDI/LNKST EEDO/LEDPRE3/SRD Name Pin No. 56 55 128 127 125 124 26 95 135 30 8 35 65 91 142 37 69 107 136 28 3 11 17 23 51 59 67 74 83 89 97 103 139 147 158 20 27 157 154 152 Name EESK/LED1/SFBD HLDA HLDAO/TCK HOLD HOLDI/TDO INTR1 INTR2/EAR INTR3/TDI INTR4/TMS JTAGSEL LB/VESA LDEV LED2/SRDCLK M/IO NC NC NC NC NC NC NC NC NC NC NC NC RDY RDYRTN RESET RXD+ RXD- SHFBUSY SLEEP TXD+ TXD- TXP+ TXP- W/R XTAL1 XTAL2 Pin No. 155 33 101 36 100 151 105 104 102 106 153 38 2 46 1 39 40 41 79 80 81 119 120 121 122 160 43 42 49 109 108 159 156 114 112 113 111 44 116 118
AM79C965A
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PIN DESIGNATIONS: 486 LOCAL BUS MODE Listed by Group
Pin Name 486/386DX Local Bus Interface A2-A31 ADS AHOLD Am486 BCLK BE0-BE3 BLAST BOFF BRDY D/C D0-D31 EADS HLDA HLDAO HOLD HOLDI INTR1 INTR2 INTR3 INTR4 JTAGSEL LB/VESA LDEV M/IO RDY RDYRTN W/R Board Interface EECS EEDI/LNKST EEDO/LEDPRE3 EESK/LED1 LED2 RESET SHFBUSY SLEEP XTAL1 XTAL2 Microwire Serial PROM Chip Select Microwire Serial EEPROM Data In/Link Status Microwire Address PROM Data Out/LED3 predriver Microwire Serial PROM Clock/LED1 LED Output Number 2 Reset Shift Busy (for external EEPROM-programmable logic) Sleep Mode Crystal Input Crystal Output O O I/O O O I O I I O O8 O8 LED LED LED LED 1 1 1 1 1 1 1 1 1 1 Address Bus Address Status Address Hold Am486 Mode Select Bus Clock Byte Enable Burst Last Backoff Burst Ready Data/Control Select Data Bus External Address Strobe Hold Acknowledge Hold Acknowledge Out Hold Request Hold Request In Interrupt Number 1 Interrupt Number 2 Interrupt Number 3 Interrupt Number 4 JTAG Select Local Bus/VESA VL-Bus Select pin Local Device Memory/I/O Select Ready Ready Return Write/Read Select IO I/O I I I I/O O I I/O I/O I/O O I I/O O I/O O I/O I/O I/O I I O I/O O I I/O TS O4 TS TS TS O8 TS TS TS TS TS TS TS TS TS TS TS TS TS 30 1 1 1 1 4 1 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin Function Type Driver No. of Pins
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AM79C965A
PIN DESIGNATIONS: 486 LOCAL BUS MODE (continued) Listed by Group
Pin Name Attachment Unit Interface (AUI) CI+/CI- DI+/DI- DO+/DO- AUI Collision Differential Pair AUI Data In Differential Pair AUI Data Out Differential Pair I I O DO 2 2 2 Pin Function Type Driver No. of Pins
Twisted-Pair Transceiver Interface (10BASE-T) RXD+/RXD- TXD+/TXD- TXP+/TXP- LNKST/EEDI Receive Differential Pair Transmit Differential Pair Transmit Predistortion Differential Pair Link Status/Microwire Serial EEPROM Data In I O O O TDO TPO LED 2 2 2 1
IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select I/O I/O I/O I/O TS TS TS TS 1 1 1 1
External Address Detection Interface (EADI) EAR SRD SRDCLK SFBD Power Supplies AVDD AVSS DVDD DVDDCLK DVDDO DVSS DVSSCLK DVSSN DVSSPAD Analog Power Analog Ground Digital Power Digital Power Clock I/O Buffer Digital Power Digital Ground Digital Ground Clock I/O Buffer Digital Ground Digital Ground Pad P P P P P P P P P 4 2 3 1 5 4 1 15 1 External Address Reject Low Serial Receive Data Serial Receive Data Clock Start Frame--Byte Delimiter I/O I/O I/O O TS TS TS LED 1 1 1 1
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PIN DESIGNATIONS: 486 LOCAL BUS MODE Driver Type
Table 9. Output Driver Types
Name TS O8 O4 OD LED Type Tri-State Totem Pole Totem Pole Open Drain LED IOL(mA) 8 8 4 8 12 -0.4 IOL(mA) -0.4 -0.4 -0.4 pF 50 50 50 50 50
Table 10. Pins with Pullups Signal TDI TMS TCK Pullup 10 K 10 K 10 K
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AM79C965A
PIN DESCRIPTION: 486 LOCAL BUS MODE Configuration Pins JTAGSEL
JTAG Function Select Input The value of this pin will asynchronously select between JTAG Mode and Multi-Interrupt Mode. The value of this pin will asynchronously affect the function of the JTAG-INTR-Daisy chain arbitration pins, regardless of the state of the RESET pin and regardless of the state of the BCLK pin. If the value is a "1", then the PCnet-32 controller will be programmed for JTAG mode. If the value is a "0", then the PCnet-32 controller will be programmed for Multi-Interrupt Mode. When programmed for JTAG mode, four pins of the PCnet-32 controller will be configured as a JTAG (IEEE 1149.1) Test Access Port. When programmed for MultiInterrupt Mode, two of the JTAG pins will become interrupts and two JTAG pins will be used for daisy chain arbitration support. Table 11 below outlines the pin changes that will occur by programming the JTAGSEL pin.
Table 11. JTAG Pin Changes
Pin JTAGSEL=1 JTAG Mode TCK TDO TDI TMS JTAGSEL=0 Multi-Interrupt Mode HLDAO HOLDI INTR3 INTR4
The JTAGSEL pin may be tied directly to VDD or VSS. A series resistor may be used but is not necessary.
LB/VESA
Local Bus/VESA VL-Bus Select Input The value of this pin will asynchronously determine the operating mode of the PCnet-32 controller, regardless of the state of RESET and regardless of the state of the BCLK pin. If the LB/VESA pin is tied to V DD, then the PCnet-32 controller will be programmed for Local Bus Mode. If the LB/VESA pin is tied to VSS, then the PCnet-32 controller will be programmed for VESA VL-Bus Mode. Note that the setting of LB/VESA determines the functionality of the following pins (names in parentheses are pins in the VESA VL-Bus Mode): Am486 (VLBEN), RESET (RESET), AHOLD (LBS16), HOLD (LREQ), HLDA(LGNT), HOLDI (LREQI), and HLDAO (LGNTO).
Am486
Am486 Mode Select resistor may be used but is not necessary. Note: This pin is used to enable bursing in the VESA VL-Bus mode when the LB/VESA pin has been tied to VSS. See the pin description for the VLBEN pin in the VESA VL-Bus Mode section. Input
The Am486 pin should be tied directly to V SS. A series
HLDAO/TCK HOLDI/TDO INTR3/TDI INTR4/TMS
Configuration Pin Settings Summary
Table 12 shows the possible pin configurations that may be i nvo ked wi th t he P Cne t- 32 c on tro ll er configuration pins.
Table 12. Configuration Pin Settings
LB/VESA 0 0 1 1 1 Am486/Am386 X* X* 0 0 1 JTAGSEL 0 1 0 1 X Mode Selected VL Bus mode with 4 interrupts and daisy chain arbitration VL Bus mode with 2 interrupts and JTAG Am486 mode with 4 interrupts and daisy chain arbitration Am486 mode with 2 interrupts and JTAG Reserved
*X = Don't care
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Table 13. Pin Connections to Power/Ground
Pin Name Pin No Supply Strapping Required Optional Required Optional Optional Required Optional Required Optional Required Optional Optional Resistive Connection to Supply Required Required Optional Required Required Optional Required Optional Required Required Required Required Recommended Resistor Size 324 in series with LED, or 10 K without LED 10 K NA 10 K 10 K NA 10 K NA 324 in series with LED, or 10 K without LED 324 in series with LED, or 10 K without LED 10 K 10 K
LED2/SRDCLK AHOLD Am486 BOFF HOLDI/TDO JTAGSEL EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP All Other Pins
2 25 31 54 100 106 152 153 154 155 156 --
Pin Connections to VDD or VSS
Several pins may be connected to V DD or V SS for various application options. Some pins are required to be connected to V DD or V SS in order to set the controller into a particular mode of operation, while other pins might be connected to VDD or VSS if that pin's function is not implemented in a specific application. Table 13 shows which pins require a connection to V DD or V SS , and which pins may optionally be connected to VDD or VSS because the application does not support that pin's function. The table also shows whether or not the connections need to be resistive.
ADS
Address Status Input/Output When driven LOW, this signal indicates that a valid bus cycle definition and address are available on the M/IO, D/C, W/R and A2-A31 pins of the local bus interface. At that time, the PCnet-32 controller will examine the combination of M/IO, D/C, W/R, and the A2-A31 pins to determine if the current access is directed toward the PCnet-32 controller. ADS will be driven LOW when the PCnet-32 controller performs a bus master access on the local bus.
AHOLD
Address Hold Input This pin is always an input. The PCnet-32 controller will put some portion of the address bus into a high impedance state whenever this signal is asserted. AHOLD may be asserted by an external cache controller when a cache invalidation cycle is being performed. AHOLD may be asserted at any time, including times when the PCnet-32 controller is the active bus master. Note that this pin is multiplexed with a VESA VL function: LBS16. Some portion of the Address Bus will be floated at the time of an address hold operation, which is signaled with the AHOLD pin. The number of Address Bus pins to be floated will be determined by the value of the Cache Line Length (CLL) register (BCR18, bits 15-11) as shown in Table 14.
Local Bus Interface A2-A31
Address Bus Input/Output Address information which is stable during a bus operation, regardless of the source. When the PCnet-32 controller is Current Master, A1-A31 will be driven. When the PCnet-32 controller is not Current Master, the A2-A31 lines are continuously monitored to determine if an address match exists for I/O slave transfers. Some portion of the Address Bus will be floated at the time of an address hold operation, which is signaled with the AHOLD pin. The number of Address Bus pins to be floated will be determined by the value of the Cache Line Length register (BCR18, bits 15-11).
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Table 14. CLL Value and Floating Address Pins
CLL Value 00000 00001 00010 00011 00100 00101-00111 01000 01001-01111 10000 10001-11111 Floated Portion of Address Bus During AHOLD None A31-A2 A31-A3 Reserved CLL Value A31-A4 Reserved CLL Values A31-A5 Reserved CLL Values A31-A6 Reserved CLL Values
BRDY
Burst Ready Input/Output BRDY functions as an input to the PCnet-32 controller during bus master cycles. When BRDY is asserted during a master cycle, it indicates to the PCnet-32 controller that the target device is accepting burst transfers. It also serves the same function as RDYRTN does for non-burst accesses. That is, it indicates that the target device has accepted the data on a master write cycle, or that the target device has presented valid data onto the bus during master read cycles. If BRDY and RDYRTN are sampled active in the same cycle, then RDYRTN takes precedence, causing the next transfer cycle to begin with a T1 cycle. BRDY functions as an output during PCnet-32 controller slave cycles and is always driven inactive (HIGH).
BCLK
Bus Clock Input Clock input that provides timing edges for all interface signals. This clock is used to drive the system bus interface and the internal buffer management unit. This clock is NOT used to drive the network functions.
BRDY is floated if the PCnet-32 controller is not being accessed as the current slave device on the local bus.
D/C
Data/Control Select Input/Output During slave accesses to the PCnet-32 controller, the D/C pin, along with M/IO and W/R, indicates the type of cycle that is being performed. PCnet-32 controller will only respond to local bus accesses in which D/C is driven HIGH by the local bus master. During PCnet-32 controller bus master accesses, the D/C pin is an output and will always be driven HIGH. D/C is floated if the PCnet-32 controller is not the current master on the local bus.
BE0-BE3
Byte Enable Input/Output These signals indicate which bytes on the data bus are active during read and write cycles. When BE3 is active, the byte on D31-D24 is valid. BE2-BE0 active indicate valid data on pins D23-D16, D15-D8, D7-D0, respectively. The byte enable signals are outputs for bus master and inputs for bus slave operations.
BLAST
Burst Last Output When the BLAST signal is asserted, then the next time that BRDY or RDYRTN is asserted, the burst cycle is complete.
D0-D31
Data Bus Input/Output Used to transfer data to and from the PCnet-32 controller to system resources via the local bus. D31-D0 are driven by the PCnet-32 controller when performing bus master writes and slave read operations. Data on D31- D0 is latched by the PCnet-32 controller when perfor mi ng bus master reads and sl ave wr ite operations. The PCnet-32 controller will always follow Am386DX byte lane conventions. This means that for word and byte accesses in which PCnet-32 controller drives the data bus (i.e. master write operations and slave read operations) the PCnet-32 controller will produce duplicates of the active bytes on the unused half of the 32bit data bus. Table 15 illustrates the cases in which duplicate bytes are created.
BOFF
Backoff Input BOFF is monitored as an input during Bus Master accesses. When PCnet-32 controller is current local bus master, it will float all appropriate bus mastering signals within 1 clock period of the assertion of BOFF. When BOFF is de-asserted, PCnet-32 controller will restart any accesses that were suspended due to the assertion of BOFF and then will proceed with other scheduled accesses, if any. Register access cannot be performed to the PCnet-32 device while BOFF is asserted.
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Table 15. Byte Duplication on Data Bus
BE3BE0 1110 1101 1011 0111 1100 1001 0011* 1000 0001 0000 DAT [31:24] Undef Undef Undef A Undef Undef D Undef D D DAT [23:16] Undef Undef A Undef Undef C C C C C DAT [15:8] Undef A Undef Copy A B B Copy D B B B DAT [7:0] A Undef Copy A Undef A Undef Copy C A Undef A
An additional local bus master may daisy-chain its HLDA signal through the PCnet-32 controller HLDAO pin. The PCnet-32 controller will deliver a HLDAO signal to the additional local bus master whenever the PCnet-32 controller receives a HLDA from the CPU, but is not simultaneously requesting the bus internally. The second local bus master must connect its HOLD output to the HOLDI input of the PCnet-32 controller in order to complete the local bus daisy-chain arbitration control. When SLEEP is not asserted, daisy chain arbitration signals that pass through the PCnet-32 controller will experience a one-clock delay from input to output (i.e. HOLDI to HOLD and HLDA to HLDAO). While SLEEP is asserted (either in snooze mode or coma mode), if the PCnet-32 controller is configured for a daisy chain (HOLDI and HLDAO signals have been selected with the JTAGSEL pin), then the system arbitration signal HLDA will be passed directly to the daisy-chain signal HLDAO without experiencing a oneclock delay. However, some combinatorial delay will be introduced in this path. Note that this pin changes polarity when VL mode has been selected (see pin description of LGNTO in VESA VL-Bus Interface section).
* Note: Byte duplication does not apply during a LBS16 access. See Table 8.
EADS
External Address Strobe Output During master write accesses in which Generate Cache Invalidation Cycles mode has been selected, the EADS pin will be asserted as part of the PCnet-32 controller cache invalidation cycle. Cache invalidation cycles will occur as often as a new cache line is reached. The cache line size can be set with the cache line length bits of BCR18 (bits [15:11]).
HOLD
Bus Hold Request Output PCnet-32 controller asserts the HOLD pin as a signal that it wishes to become the local bus master. HOLD is active high. Once asserted, HOLD remains active until HLDA has become active, independent of subsequent assertion of SLEEP or setting of the STOP bit or access to the S_RESET port (offset 14h). Note t hat this pin changes polarity when the VL mode is selected (see pin description of LREQ in VESA VLBus Interface section).
HLDA
Bus Hold Acknowledge Input PCnet-32 controller examines the HLDA signal to determine when it has been granted ownership of the bus. HLDA is active HIGH. When HLDA is asserted and HOLD is being asserted by the PCnet-32 controller, the PCnet-32 controller assumes ownership of the local bus. However, if the PCnet-32 controller is asser ting HOLD because HOLDI is asserted (as in a daisy chain arbitration), then PCnet-32 controller will assert HLDAO and will not assume ownership of the local bus. Note that it changes polarity when the VL mode is selected (see pin description of LGNT in VESA VL-Bus Interface section).
HOLDI
Bus Hold Request In Input This signal is multiplexed with the TDO pin, and is available only when the Multi-Interrupt mode has been selected with the JTAGSEL pin. An additional local bus master may daisy-chain its bus hold request signal through the PCnet-32 controller HOLDI pin. The PCnet-32 controller will convey the HOLDI request to the CPU via the PCnet-32 controller HOLD output. The second local bus master must connect its HLDA input to the HLDAO output of the PCnet-32 controller in order to complete the local bus daisy-chain arbitration control. When SLEEP is not asserted, daisy chain arbitration signals that pass through the PCnet-32 controller will
HLDAO
Bus Hold Acknowledge Out Output This signal is multiplexed with the TCK pin, and is available only when the Multi-Interrupt mode has been selected with the JTAGSEL pin.
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experience a one-clock delay from input to output (i.e. HOLDI to HOLD and HLDA to HLDAO). While SLEEP is asserted (either in snooze mode or coma mode), if the PCnet-32 controller is configured for a daisy chain (HOLDI and HLDAO signals have been selected with the JTAGSEL pin), then the daisychain signal HOLDI will be passed directly to the system arbitration signal HOLD without experiencing a one-clock delay. However, some combinatorial delay will be introduced in this path. If Multi-Interrupt mode has been selected and the daisy-chain arbitration feature is not used, then the HOLDI input should be tied to VSS through a resistor. Note that this pin changes polarity when VL mode has been selected (see pin description of LREQI in VESA VL-Bus Interface section).
programmed for level-sensitive or edge-sensitive operation. PCnet-32 controller interrupt pins will be floated at H_RESET and will remain floated until either the EEPROM has been successfully read, or, following an EEPROM read failure, a Software Relocatable Mode sequence has been successfully executed.
LDEV
Local Device Output LDEV is driven by the PCnet-32 controller when it recognizes an access to PCnet-32 controller I/O space. Such recognition is dependent upon a valid sampled ADS strobe plus valid M/IO, D/C and A31-A5 values.
M/IO
Memory I/O Select Input/Output During slave accesses to the PCnet-32 controller, the M/IO pin, along with D/C and W/R, indicates the type of cycle that is being performed. PCnet-32 controller will only respond to local bus accesses in which M/IO is sampled as a zero by the PCnet-32 controller. During PCnet-32 controller bus master accesses, the M/IO pin is an output and will always be driven high. M/IO is floated if the PCnet-32 controller is not the current master on the local bus.
INTR1-INTR4
Interrupt Request Output An attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR, RINT, IDON, MFCO, RCVCCO, TXSTRT, or JAB. Each of these status flags has a mask bit which allows for
suppression of INTR assertion. These flags have the meaning shown in Table 16. Table 16. Status Flags
BABL MISS MERR RINT IDON MFCO Babble (CSR0, bit 14) Missed Frame (CSR0, bit 12) Memory Error (CSR0, bit 11) Receive Interrupt (CSR0, bit 10) Initialization Done (CSR0, bit 8) Missed Packet Count Overflow (CSR4, bit 9) Receive Collision Count Overflow (CSR4, bit 5) Transmit Start (CSR4, bit 3) Jabber (CSR4, bit 1)
RESET
System Reset Input When RESET is asserted high and the LB/VESA pin has been tied to VDD, then the PCnet-32 controller perfor ms an inter nal system reset of the type H_RESET (HARDWARE_ RESET). The RESET pin must be held for a minimum of 30 BCLK periods. While in the H_RESET state, the PCnet-32 controller will float or de-assert all outputs. Note that this pin changes polarity when VL mode has been selected (see pin description of RESET in VESA VL-Bus Interface section).
RCVCCO
TXSTRT JAB
RDY
Ready Output RDY functions as an output from the PCnet-32 controller during PCnet-32 controller slave cycles. During PCnet-32 controller slave read cycles, RDY is asserted to indicate that valid data has been presented on the data bus. During PCnet-32 controller slave write cycles, RDY is asserted to indicate that the data on the data bus has been internally latched. RDY is asserted for one BCLK period. RDY is then driven high for onehalf of one clock period before being released. RDY is floated if the PCnet-32 controller is not the current slave on the local bus.
Note that there are four possible interrupt pins, depending upon the mode that has been selected with the JTAGSEL pin. Only one interrupt pin may be used at one time. The active interrupt pin is selected by programming the interrupt select register (BCR21). The default setting of BCR121will select interrupt INTR1 as the active interrupt. Note that BCR21 is EEPROMprogrammable. Inactive interrupt pins are floated. The polarity of the interrupt signal is determined by the INTLEVEL bit of BCR2. The interrupt pins may be
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In systems where both RDY and RDYRTN (or equivalent) signals are provided, RDY must NOT be tied to RDYRTN. Most systems now provide for a local device ready input to the memory controller that is separate from the CPU READY signal. This second READY signal is usually labeled as READYIN. This signal should be connected to the PCnet-32 controller RDY signal. The CPU READY signal should be connected to the PCnet-32 controller RDYRTN pin. In systems where only one READY signal is provided, then RDY may be tied to RDYRTN.
During PCnet-32 controller bus master accesses, the W/R pin is an output. W/R is floated if the PCnet-32 controller is not the current master on the local bus.
Board Interface LED1
LED1 Output This pin is shared with the EESK function. When operating as LED1, the function and polarity on this pin are programmable through BCR5. The LED1 output from the PCnet-32 controller is capable of sinking the necessary 12 mA of current to drive an LED directly. The LED1 pin is also used during EEPROM Autodetection to determine whether or not an EEPROM is present at the PCnet-32 controller microwire interface. At the trailing edge of RESET, this pin is sampled to determine the value of the EEDET bit in BCR19. A sampled HIGH value means that an EEPROM is present, and EEDET will be set to ONE. A sampled LOW value means that an EEPROM is not present, and EEDET will be set to ZERO. See the "EEPROM Autodetection" section for more details. If no LED circuit is to be attached to this pin, then a pullup or pull-down resistor must be attached instead, in order to resolve the EEDET setting.
RDYRTN
Ready Return Input RDYRTN functions as an input to the PCnet-32 control ler. RDYRTN is used to terminate all master accesses
performed by the PCnet-32 controller, except that linear burst transfers may also be terminated with the BRDY signal. RDYRTN is used to terminate slave read accesses to PCnet-32 controller I/O space.
When asser ted dur ing slave read accesses to PCnet-32 controller I/O space, RDYRTN indicates that the bus mastering device has seen the RDY that was generated by the PCnet-32 controller and has accepted the PCnet-32 controller slave read data. Therefore, PCnet-32 controller will hold slave read data on the bus until it synchronously samples the RDYRTN input as active low. The PCnet-32 controller will not hold RDY valid asserted during this time. The duration of the RDY pulse generated by the PCnet-32 controller will always be a single BCLK cycle. RDYRTN is ignored during slave write accesses to PCnet-32 controller I/O space. Slave write accesses to PCnet-32 controller I/O space are considered terminated by the PCnet-32 controller at the end of the cycle during which the PCnet-32 controller issues an active RDY. In systems where both a RDY and RDYRTN (or equivalent) signals are provided, then RDY must not be tied to RDYRTN. Most systems now provide for a local device ready input to the memory controller that is separate from the CPU READY signal. This second READY signal is usually labeled as READYIN. This signal should be connected to the PCnet-32 controller RDY signal. The CPU READY signal should be connected to the PCnet-32 controller RDYRTN pin. In systems where only one READY signal is provided, then the PCnet-32 controller RDY output may be tied to the PCnet-32 controller RDYRTN input.
LED2
LED2 Output This pin is shared with the SRDCLK function. When operating as LED2, the function and polarity on this pin are programmable through BCR6. The LED2 output from the PCnet-32 controller is capable of sinking the necessary 12 mA of current to drive an LED directly. This pin also selects address width for Software Relocatable Mode. When this pin is HIGH during Software Relocatable Mode, then the device will be programmed to use 32 bits of addressing while snooping accesses on the bus during Software Relocatable Mode. When this pin is LOW during Software Relocatable Mode, then the device will be programmed to use 24 bits of addressing while snooping accesses on the bus during Software Relocatable Mode. The upper 8 bits of address will be assumed to match during the snooping operation when LED2 is LOW. The 24-bit addressing mode is intended for use in systems that employ the GPSI signals. For more information on the GPSI function see section General Purpose Serial Interface. If no LED circuit is to be attached to this pin, then a pull up or pull down resistor must be attached instead, in order to resolve the Software Relocatable Mode address setting.
W/R
Write/Read Select Input/Output During slave accesses to the PCnet-32 controller, the W/R pin, along with D/C and M/IO, indicates the type of cycle that is being performed.
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LEDPRE3
LEDPRE3 Output
This pin is shared with the EEDO function. When operating as LEDPRE3, the function and polarity on this pin are programmable through BCR7. This signal is labeled as LED " PRE" 3 because of the multi-function nature of this pin. If an LED circuit were directly attached to this pin, it would create an IOL requirement that could not be met by the serial EEPROM that would also be attached to this pin. Therefore, if this pin is to be used as an additional LED output while an EEPROM is used in the system, then buffering is required between the LEDPRE3 pin and the LED circuit. If no EEPROM is included in the system design, then the LEDPRE3 signal may be directly connected to an LED without buffering. The LEDPRE3 output from the PCnet-32 controller is capable of sinking the necessary 12 mA of current to drive an LED in this case. For more details regarding LED connection, see the section on LEDs.
SLEEP
Sleep Input When SLEEP input is asserted (active LOW), the PCnet-32 controller performs an internal system reset and then proceeds into a power savings mode. (The reset operation caused by SLEEP assertion will not affect BCR registers.) All outputs will be placed in their nor mal reset condition. During sleep mode, all PCnet-32 controller inputs will be ignored except for the SLEEP pin itself. De-assertion of SLEEP results in wake-up. The system must refrain from starting the network operations of the PCnet-32 controller for 0.5 seconds following the de-assertion of the SLEEP signal in order to allow internal analog circuits to stabilize. Both BCLK and XTAL1 inputs must have valid clock signals present in order for the SLEEP command to take effect. If SLEEP is asserted while LREQ/HOLD is asserted, then the PCnet-32 controller will perform an internal system reset and then wait for the assertion of LGNT/ HLDA. When LGNT/HLDA is asserted, the LREQ/ HOLD signal will be de-asserted and then the PCnet32 controller will proceed to the power savings mode. Note that the internal system reset will not cause the HOLD/LREQ signal to be de-asserted. The SLEEP pin should not be asserted during power supply ramp-up. If it is desired that SLEEP be asserted at power up time, then the system must delay the assertion of SLEEP until three BCLK cycles after the completion of a valid pin RESET operation.
LNKST
LINK Status Output This pin provides 12 mA for driving an LED. It indicates an active link connection on the 10BASE-T interface. The signal is programmable through BCR4. Note that this pin is multiplexed with the EEDI function. This pin remains active in snooze mode.
SHFBUSY
Shift Busy Output The function of the SHFBUSY signal is to indicate when the last byte of the EEPROM contents has been shifted out of the EEPROM on the EEDO signal line. This information is useful for external EEPROMprogrammable registers that do not use the microwire protocol, as is described herein: When the PCnet-32 controller is performing a serial read of the EEPROM through the microwire interface, the SHFBUSY signal will be driven HIGH. SHFBUSY can serve as a serial shift enable to allow the EEPROM data to be serially shifted into an external device or series of devices. The SHFBUSY signal will remain actively driven HIGH until the end of the EEPROM read operation. If the EEPROM checksum was verified, then the SHFBUSY signal will be driven LOW at the end of the EEPROM read operation. If the EEPROM checksum verification failed, then the SHFBUSY signal will remain HIGH. This function effectively demarcates the end of a successful EEPROM read operation and therefore is useful as a programmable-logic low-active output enable signal. For more details on external EEPROMprogrammable registers, see the EEPROM Microwire Access section under Hardware Access. This pin can be controlled by the host system by writing to BCR19, bit 3 (EBUSY).
XTAL1-XTAL2
Crystal Oscillator Inputs Input/Output The crystal frequency determines the network data rate. The PCnet-32 controller supports the use of quar tz crystals to generate a 20 MHz frequency compatible with the ISO 8802-3 (IEEE/ANSI 802.3) network frequency tolerance and jitter specifications. See the section External Crystal Characteristics (in section Manchester Encoder/ Decoder) for more detail. The network data rate is one-half of the crystal frequency. XTAL1 may alternatively be driven using an external CMOS level source, in which case XTAL2 must be left unconnected. Note that when the PCnet-32 controller is in coma mode, there is an internal 22 KW resistor from XTAL1 to ground. If an external source drives XTAL1, some power will be consumed driving this resistor. If XTAL1 is driven LOW at this time power consumption will be minimized. In this case, XTAL1 must remain active for at least 30 cycles after the assertion of SLEEP and de-assertion of HOLD.
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Microwire EEPROM Interface EESK
EEPROM Serial Clock Output The EESK signal is used to access the external ISO 8802-3 (IEEE/ANSI 802.3) address PROM. This pin is designed to directly interface to a serial EEPROM that uses the microwire interface protocol. EESK is connected to the microwire EEPROM's Clock pin. It is controlled by either the PCnet-32 controller directly during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 1. EESK can be used during programming of external EEPROM-programmable registers that do not use the microwire protocol as follows: When the PCnet-32 controller is performing a serial read of the IEEE Address EEPROM through the microwire interface, the SHFBUSY signal will serve as a serial shift enable to allow the EEPROM data to be serially shifted into an external device or series of devices. This same signal can be used to gate the output of the programmed logic to avoid the problem of releasing intermediate values to the rest of the system board logic. The EESK signal can serve as the clock, and EEDO will serve as the input data stream to the programmable shift register.
The EECS signal is active high. It is controlled by either the PCnet-32 controller during a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 2.
EEDI
EEPROM Data In Output The EEDI signal is used to access the external ISO 8802-3 (IEEE/ANSI 802.3) address PROM. EEDI functions as an output. This pin is designed to directly interface to a serial EEPROM that uses the microwire interface protocol. EEDI is connected to the microwire EEPROM's Data Input pin. It is controlled by either the PCnet-32 controller during command portions of a read of the entire EEPROM, or indirectly by the host system by writing to BCR19, bit 0.
Attachment Unit Interface CI
Collision In Input A differential input pair signaling the PCnet-32 controller that a collision has been detected on the network media, indicated by the CI inputs being driven with a 10 MHz pattern of sufficient amplitude and pulse width to meet ISO 8802-3 (IEEE/ANSI 802.3) standards. Operates at pseudo ECL levels.
EEDO
EEPROM Data Out Input The EEDO signal is used to access the external ISO 8802-3 (IEEE/ANSI 802.3) address PROM. This pin is designed to directly interface to a serial EEPROM that uses the microwire interface protocol. EEDO is connected to the microwire EEPROM's Data Output pin. It is controlled by the EEPROM during reads. It may be read by the host system by reading BCR19, bit 0. EEDO can be used during programming of external EEPROM-programmable registers that do not use the microwire protocol as follows: When the PCnet-32 controller is performing a serial read of the IEEE Address EEPROM through the microwire interface, the SHFBUSY signal will serve as a serial shift enable to allow the EEPROM data to be serially shifted into an external device or series of devices. This same signal can be used to gate the output of the programmed logic to avoid the problem of releasing intermediate values to the rest of the system board logic. The EESK signal can serve as the clock, and EEDO will serve as the input data stream to the programmable shift register.
DI
Data In Input A differential input pair to the PCnet-32 controller carrying Manchester encoded data from the network. Operates at pseudo ECL levels.
DO
Data Out Output
A differential output pair from the PCnet-32 controller for transmitting Manchester encoded data to the network. Operates at pseudo ECL levels.
Twisted Pair Interface RXD
10BASE-T Receive Data 10BASE-T port differential receivers. Input
TXD
10BASE-T Transmit Data 10BASE-T port differential drivers. Output
TXP
10BASE-T Pre-distortion Control Output These outputs provide transmit predistortion control in conjunction with the 10BASE-T port differential drivers.
EECS
EEPROM Chip Select Output The function of the EECS signal is to indicate to the microwire EEPROM device that it is being accessed.
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External Address Detection Interface
The EADI interface is enabled through BCR2, bit 3 (EADISEL).
General Purpose Serial Interface
The GPSI interface is selected through the PORTSEL bits of the Mode register (CSR15) and enabled through the TSTSHDW[1] bit (BCR18) or the GPSIEN bit (CSR124). Note that when GPSI test mode is invoked, slave address decoding must be restricted to the lower 24 bits of the address bus by setting the IOAW24 bit in BCR2 and by pulling LED2 LOW during Software Reloactable Mode. The upper 8 bits of the address bus will always be considered matched when examining incoming I/O addresses. During master accesses while in GPSI mode, the PCnet-32 controller will not drive the upper 8 bits of the address bus with address information. See the GPSI section for more detail.
EAR
External Address Reject Low Input An EADI input signal. The incoming frame will be checked against the internally active address detection mechanisms and the result of this check will be OR'd with the value on the EAR pin. The EAR pin is defined as REJECT. See the EADI section for details regarding the function and timing of this signal. Note that this pin is multiplexed with the INTR2 pin.
SFBD
Start Frame-Byte Delimiter Output Start Frame-Byte Delimiter Enable. EADI output signal. An initial rising edge on this signal indicates that a start of frame delimiter has been detected. The serial bit stream will follow on the SRD signal, commencing with the destination address field. SFBD will go high for 4 bit times (400 ns) after detecting the second "1" in the SFD (Start of Frame Delimiter) of a received frame. SFBD will subsequently toggle every 400 ns (1.25 MHz frequency) with each rising edge indicating the first bit of each subsequent byte of the received serial bit s t r e a m . S F B D w i l l b e i n a c t i ve d u r i n g f r a m e transmission. Note that this pin is multiplexed with the LED1 pin.
TXDAT
Transmit Data Input/Output TXDAT is an output, providing the serial bit stream for transmission, including preamble, SFD data and FCS field, if applicable. Note that the TxDAT pin is multiplexed with the A31 pin.
TXEN
Transmit Enable Input/Output TXEN is an output, providing an enable signal for transmission. Data on the TXDAT pin is not valid unless the TXEN signal is HIGH. Note that the TXEN pin is multiplexed with the A30 pin.
STDCLK
Serial Transmit Data Clock Input STDCLK is an input, providing a clock signal for MAC activity, both transmit and receive. Rising edges of the STDCLK can be used to validate TXDAT output data. The STDCLK pin is multiplexed with the A29 pin. Note that this signal must meet the frequency stability requirement of the ISO 8802-3 (IEEE/ANSI 802.3) specification for the crystal.
SRD
Serial Receive Data Output An EADI output signal. SRD is the decoded NRZ data from the network. This signal can be used for external address detection. Note that when the 10BASE-T port is selected, transitions on SRD will only occur during receive activity. When the AUI port is selected, transitions on SRD will occur during both transmit and receive activity. Note that this pin is multiplexed with the LEDPRE3 pin.
CLSN
Collision Input/Output CLSN is an input, indicating to the core logic that a collision has occurred on the network. Note that the CLSN pin is multiplexed with the A28 pin.
SRDCLK
Serial Receive Data Clock Output An EADI output signal. Serial Receive Data is synchronous with reference to SRDCLK. Note that when the 10BASE-T port is selected, transitions on SRDCLK will only occur during receive activity. When the AUI port is selected, transitions on SRDCLK will occur during both transmit and receive activity. Note that this pin is multiplexed with the LED2 pin.
RXCRS
Receive Carrier Sense Input/Output RXCRS is an input. When this signal is HIGH, it indicates to the core logic that the data on the RXDAT input pin is valid.
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Note that the RXCRS pin is multiplexed with the A27 pin.
SRDCLK
Serial Receive Data Clock Input/Output SRDCLK is an input. Rising edges of the SRDCLK signal are used to sample the data on the RXDAT input whenever the RXCRS input is HIGH. Note that the SRDCLK pin is multiplexed with the A26 pin.
avoid excessive noise on these lines. Refer to Appendix B and the PCnet Family Technical Manual (PID# 18216A) for details.
AVSS
Analog Ground (2 Pins) Power There are two analog ground pins. Special attention should be paid to the printed circuit board layout to avoid excessive noise on these lines. Refer to Appendix B and to the PCnet Family Technical Manual for details.
RXDAT
Receive Data Input/Output RXDAT is an input. Rising edges of the SRDCLK signal are used to sample the data on the RXDAT input whenever the RXCRS input is HIGH. Note that the RXDAT pin is multiplexed with the A25 pin.
DVDD
Digital Power (3 Pins) Power There are 3 digital power supply pins. (DVDD1, DVDD2, and DVDD3) used by the internal circuitry.
DVDDCLK
Digital Power Clock (1 Pin) circuitry. Power
This pin is used to supply power to the clock buffering
IEEE 1149.1 Test Access Port Interface TCK
Test Clock Input The clock input for the boundary scan test mode operation. TCK can operate up to 10 MHz. If left unconnected this pin has a default value of HIGH.
DVDDO
I/O Buffer Digital Power (5 Pins) Power There are 5 digital power supply pins (DVDD01- DVDD05) used by Input/Output buffer drivers.
TDI
Test Data Input Input The test data input path to the PCnet-32 controller. If left unconnected, this pin has a default value of HIGH.
DVSS
Digital Ground (4 Pins) Ground There are 4 digital ground pins (DVSS1-DVSS4) used by the internal digital circuitry.
TDO
Test Data Output Output The test data output path from the PCnet-32 controller. TDO is floated when the JTAG port is inactive.
DVSSCLK
Digital Ground Clock (1 Pin) Ground This pin is used to supply a ground to the clock buffering circuitry.
TMS
Test Mode Select Input A serial input bit stream is used to define the specific boundary scan test to be executed. If left unconnected, this pin has a default value of HIGH.
DVSSN
I/O Buffer Digital Ground (15 Pins) Ground These 15 ground pins (DVSSN1-DVSSN15) are used by the Input/Output buffer drivers.
DVSSPAD
Digital Ground Pad (1 Pin) Ground This pin is used by the Input/Output logic circuits.
Power Supply Pins AVDD
Analog Power (4 Pins) Power There are four analog +5 V supply pins. Special attention should be paid to the printed circuit board layout to
44
AM79C965A
BASIC FUNCTIONS System Bus Interface Function
The PCnet-32 controller is designed to operate as a Bus Master during normal operations. Some slave accesses to the PCnet-32 controller are required in normal operations as well. Initialization of the PCnet-32 controller is achieved through a combination of Bus Slave accesses, Bus Master accesses and an optional read of a serial EEPROM that is performed by the PCnet-32 controller. The EEPROM read operation is performed through the microwire interface. The ISO 8802-3 (IEEE/ANSI 802.3) Ethernet Address may reside within the serial EEPROM. Some PCnet-32 controller configuration registers may also be programmed by the EEPROM read operation. The address PROM, on-chip board-configuration registers, and the Ethernet controller registers occupy 32 bytes of I/O space which can be located by modifying the I/O base address register. The default base address can be written to the EEPROM. The PCnet-32 controller will automatically read the I/O Base Address from the EEPROM after H_RESET, or at any time that the software requests that the EEPROM should be read. When no EEPROM is attached to the serial microwire interface, the PCnet-32 controller detects the condition, and enters Software Relocatable Mode. While in Software Relocatable Mode, the PCnet-32 controller will not respond to any bus accesses, but will snoop the bus for accesses to I/O address 378h. When a successfully executed and uninterrupted sequence of write operations is seen at this location, the PCnet-32 controller will accept the next sequence of accesses as carrying I/O Base Address relocation and interrupt pin programming information. After this point, the PCnet-32 controller will begin to respond directly to accesses directed toward offsets from the newly loaded I/O Base Address. This scheme allows for jumper less relocatable I/O implementations.
controller occupies 32 bytes of I/O space that must begin on a 32-byte block boundary. The I/O Base Address can be changed to any 32-bit quantity that begins on a 32-byte block boundary through the function of the Software Relocatable Mode. It can also be changed to any 32-bit value that begins on a 32-byte block boundary through the automatic EEPROM read operation that occurs immediately after the H_RESET fu n c ti o n h a s c o mp l et ed . Th is r ea d o pe ra ti o n automatically alters the I/O Base Address of the PCnet-32 controller. The 32-byte I/O space is used by the software to program the PCnet-32 controller operating mode, to enable and disable various features, to monitor operating status and to request particular functions to be executed by the PCnet-32 controller. The other portion of the software interface is the descriptor and buffer areas that are shared between the software and the PCnet-32 controller during normal network operations. The descriptor area boundaries are set by the software and do not change during normal network operations. There is one descriptor area for receive activity and there is a separate area for transmit activity. The descriptor space contains relocatable pointers to the network packet data and it is used to transfer packet status from the PCnet-32 controller to the software. The buffer areas are locations that hold packet data for transmission or that accept packet data that has been received.
Network Interfaces
The PCnet-32 controller can be connected to an 802.3 network via one of two network interfaces. The Attachment Unit Interface (AUI) provides an ISO 8802-3 (IEEE/ANSI 802.3) compliant differential interface to a rem ote MAU or an on- board transcei ver. The 10BASE-T interface provides a twisted-pair Ethernet port. While in auto-selection mode, the interface in use is determined by an auto-sensing mechanism which checks the link status on the 10BASE-T port. If there is no active link status, then the device assumes an AUI connection.
Software Interface
The software interface to the PCnet-32 controller is divided into two parts. One part is the direct access to the I/O resources of the PCnet-32 controller. The PCnet-32
DETAILED FUNCTIONS Bus Interface Unit
The bus interface unit is built of several state machines that run synchronously to BCLK. One bus interface unit state machine handles accesses where the PCnet-32 controller is the bus slave, and another handles accesses where the PCnet-32 controller is the bus master. All inputs are synchronously sampled except ADS, M/IO, D/C, W/R and the A[31:5] bus when this
bus is an input to the PCnet-32 controller. All outputs are synchronously generated on the rising edge of BCLK with the following exceptions: LDEV is generated asynchronously. RDY is driven/floated on falling edges of BCLK, but will change state on rising edges of BCLK.
AM79C965A
45
The following sections describe the various bus master and bus slave operations that will be performed by the PCnet-32 controller. The timing diagrams that are included in these sections (Bus Acquisition section through Slave Timing section) show the signals and timings of the Am486 32-bit mode of operation. The sections from Bus Acquisition through Linear Burst DMA Transfers show bus master operations. The Slave Timing section shows bus slave operations. Note that the PCnet-32 controller operation in Am486 32-bit mode represents a merger of the requirements of the V E S A V L - B u s s p e c i f i c a t i o n a n d A m 4 8 6 bu s specification, whichever is more stringent. The concepts discussed in the following sections and the basic nature of the timings shown is applicable in a general sense to PCnet-32 controller operational modes. For specific differences in timing between modes and for examples of timing diagrams showing basic transfers in each of the modes, please consult the following sections: Am486 32-bit mode: VESA VL-Bus mode: Bus Acquisition section through Slave Timing section VESA VL-Bus Mode Timing section
this case, the point of division between the two groups of address pins will depend upon the value of LINBC in BCR18. In all other timing diagrams, the two groups are shown separately just to maintain consistency with the AHOLD and Linear Burst timing diagrams. For more details, see the AHOLD and Linear Burst Count sections.
Bus Acquisition
The PCnet-32 controller microcode (in the buffer management section) will determine when a DMA transfer should be initiated. The first step in any PCnet-32 controller bus master transfer is to acquire ownership of the bus. This task is handled by synchronous logic within the BIU. Bus ownership is requested with the HOLD signal and ownership is granted by the CPU (or an arbiter) through the HLDA signal. The PCnet-32 controller additionally supplies HOLDI and HLDAO signals to allow daisy chaining of devices through the PCnet-32 controller. Priority of the HOLDI input versus the PCnet-32 controller's own internal request for bus mastership can be set using the PRPCNET bit of BCR17. Simple bus arbitration (HOLD, HLDA only) is shown in Figure 1. Note that assertion of the STOP bit will not cause a deassertion of the HOLD signal. Note also that a read of the S_RESET register (I/O resource at offset 14h from the PCnet-32 controller base I/O address) will not cause a de-assertion of the HOLD signal. Either of these actions will cause the internal master state machine logic to cease operations, but the HOLD signal will remain active until the HLDA signal is synchronously sampled as asserted. Following either of the above actions, on the next clock cycle after the HLDA signal is synchronously sampled as asserted, the PCnet-32 controller will de-assert the HOLD signal. No bus master accesses will have been performed during this brief bus ownership period.
For selection of each mode, consult the section on Configuration Pins in the Pin Description section. Note that all timing diagrams in this document have been drawn showing reference to two groups of address pins: namely, A4-A31 and A2-A3, BE0-BE3. In the AHOLD timing diagrams, the two groups are shown separately, because the upper address pins become floated, while the lower address pins do not. The point of division between the two groups of address pins will depend upon the value of CLL in BCR18. In the case of Linear Burst operations, the upper address pins are shown separately because that group does not change its value through a single linear burst, while the lower address pins do change value. In
46
AM79C965A
Ti BCLK
Ti
Ti
Ti
Tt
T1
T2
T2
ADS A4-A31, M/IO, D/C
W/R A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
From PCnet-32
D0-D31
HOLD
HLDA
18219-5
Figure 1. Bus Acquisition
Assertion of a minimum-width pulse on the RESET pin will cause the HOLD signal to de-assert within six clock cycles following the assertion of the RESET pin. In this case, the PCnet-32 controller will not wait for the assertion of the HLDA signal before de-asserting the HOLD signal. This description of behavior is identical for the VESA VL-Bus mode of operation, except that the HOLD, HLDA and RESET signals are replaced by the inverted sense signals LREQ, LGNT, and RESET, respectively;
the BCLK, BOFF, EADS, and RDY signals are replaced by LCLK, WBACK, LEADS, and LRDY, respectively.
Bus Master DMA Transfers
There are three primary types of DMA transfers. All DMA transfers will have wait states inserted until either RDYRTN or BRDY is asserted. Figure 2 and Figure 3 show the basic bus transfers of read and write without ready wait states and then with ready wait states.
AM79C965A
47
Ti BCLK
Ti
T1
T2
T1
T2
T1
T2
T2
T2
Ti
Ti
ADS A4-A31, M/IO, D/C
W/R A2-A3, BE0 BE3 RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32
D0 D31
HOLD
HLDA
18219-6
Figure 2. Basic Read Cycles without and with Wait States
48
AM79C965A
Ti BCLK
Ti
T1
T2
T1
T2
T1
T2
T2
T2
Ti
Ti
ADS A4 A31, M/IO, D/C
W/R A2 A3, BE0 BE3 RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32
D0 D31
HOLD
HLDA
18219-7
Figure 3. Basic Write Cycles without and with Wait States
AM79C965A
49
Effect of BOFF Assertion of BOFF during bus master transfers will cause the PCnet-32 controller to float all of its bus signals beginning at the next clock cycle. Any access which has been interrupted by BOFF will be restarted
when the BOFF signal is de-asserted. Simultaneous assertion of RDYRTN (or BRDY) and BOFF is resolved in favor of BOFF. The RDYRTN (or BRDY) is ignored for such a cycle, and when BOFF is de-asserted, the cycle is restarted. See Figure 4 for detail.
Ti BCLK
Ti
T1
T2
T2
Tb
Tb
T1b T2
T2
Ti
Ti
ADS A4-A31, M/IO, D/C W/R A2-A3, BE0 -BE3 RDYRTN 100 100 100 100
BRDY
BLAST
To PCnet-32 To PCnet-32
D0-D31
BOFF
HOLD
HLDA
18219-8
Figure 4. Restarted Read Cycle
50
AM79C965A
Effect of AHOLD Assertion of AHOLD during bus master transfers will cause the PCnet-32 controller to float some portion of the address bus beginning at the next clock cycle. If RDYRTN is returned while AHOLD is active, then the cycle completes, since the data bus may remain active during AHOLD. However, a new cycle will not be started while AHOLD is active. The portion of the Address Bus that will be floated at the time of an address hold operation will be determined by the value of the Cache Line Length register (BCR18, bits 15-11). Table 17 lists all of the legal values of CLL showing the portion of the Address Bus that will become floated during an address hold operation. If the RDYRTN signal is not returned while AHOLD is active, then the PCnet-32 controller will resume driving the same address onto the address bus when AHOLD is released. The PCnet-32 controller will not reissue the ADS signal at this time. See Figure 5 and Figure 6 for
details.
Table 17. CLL Value and Floating Address Pins
CLL Value Floated Portion of Address Bus During AHOLD None A31-A2 A31-A3 Reserved CLL Value A31-A4 Reserved CLL Values A31-A5 Reserved CLL Values A31-A6 Reserved CLL Values
00000 00001 00010 00011 00100 00101-00111 01000 01001-01111 10000 10001-11111
Note: The default value of CLL after H_RESET is
00100. All timing diagrams in this document are drawn with the assumption that this is the value of CLL.
AM79C965A
51
Ti BCLK
Ti
T1
T2
T2
T2
Ti
Ti
T1
T2
Ti
Ti
ADS A4-A31 100 104
M/IO, D/C
W/R A2-A3, BE0 -BE3 RDYRTN 100 104
BRDY
BLAST
To PCnet-32 To PCnet-32
D0-D31
AHOLD
HOLD
HLDA
18218-9
Figure 5. Read Cycle with AHOLD Note that initial access is allowed to complete in spite of AHOLD, but next access is prevented from beginning until AHOLD is de-asserted.
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AM79C965A
Ti BCLK
Ti
T1
T2
T2
T2
T2
T2
T1
T2
Ti
Ti
ADS A4-A31 100 100 104
M/IO , D/C
W/R A2-A3, BE0-BE3 RDYRTN 100 104
BRDY
BLAST
To PCnet-32 To PCnet-32
D0-D31
AHOLD
HOLD
HLDA
18219-80
Figure 6. Read Cycle with AHOLD Address is re-driven when AHOLD is de-asserted, since RDYRTN had not yet arrived.
Effect of Bus Preemption If a bus preemption event occurs during a basic transfer cycle, then the behavior of the PCnet-32 controller will depend upon which specific type of access is being performed. The general response of the PCnet-32 controller is that the current operation will complete before the PCnet-32 controller relinquishes the bus in response to the preemption. "Current operation" in this sense refers to the general PCnet-32 controller operation, such as "descriptor access". Note that a "descriptor access" consists of one or two basic transfers. Therefore, both transfers of a descriptor access must be completed before the bus will be released in response to a preemption. See each of the sections for Initialization Block DMA transfers, Descriptor DMA transfers, FIFO DMA transfers and Linear Burst Transfers for more specific information.
AM79C965A
53
Effect of LBS16 (VL-Bus mode only) Dynamic bus sizing is recognized by the PCnet-32 controller while operating in the VL-Bus mode. The LBS16 signal is used to indicate to the PCnet-32 controller whether the VL-Bus target is a 16-bit or 32-bit peripheral. When the target device indicates that it is 16 bits in width by asserting the LBS16 signal at least one LCLK period before asserting the RDYRTN signal, then the PCnet-32 controller will dynamically respond to the size constraints of the peripheral by performing additional accesses. Table 18 shows the sequence of accesses that will be performed by the PCnet-32 controller in response to the assertion of LBS16. Figure 7 shows an example of an exchange between a 16-bit VL-Bus peripheral and the PCnet-32 controller. Note that the LBS16 signal is asserted during the LCLK
that precedes the assertion of RDYRTN. In this particular case, in order to maintain zero-wait state accesses, the 16-bit target must generate LBS16 in a very short time in order to meet the required setup time of LBS16 into the PCnet-32 controller. If the peripheral were incapable of meeting the required setup time, then a wait state would be needed in order to insure that LBS16 is asserted at least one LCLK prior to the assertion of the RDYRTN signal. When the assertion of LBS16 during a PCnet-32 controller master access has created the need for a second access as specified in the table above, and the WBACK signal becomes active during the second access, then, when WBACK is de-asser ted, the PCnet-32 controller will repeat both accesses of the pair.
Table 18. Data Transfer Sequence from 32-Bit Wide to 16-Bit Wide
Current Access BE3 1 1 1 0 1 1 0 1 0 0 BE2 1 1 0 0 1 0 0 0 0 1 BE1 1 0 0 0 0 0 0 1 1 1 BE0 0 0 0 0 1 1 1 1 1 1 BE3 NR* NR* 1 0 NR* 1 0 NR* NR* NR* 0 0 1 1 1 1 0 0 1 1 1 1 Next with LBS16 BE2 BE1 BE0
*NR = No second access Required for these cases
54
AM79C965A
Ti LCLK
Ti
T1
T2
T1
T2
Ti
Ti
Ti
Ti
Ti
ADS ADR4- ADR31 M/IO, D/C 100 100
W/R ADR2 ADR3, BE2 BE3 BE0 BE1 100 100
RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32
DAT0 DAT31 LBS16
LREQ
LGNT
18219-10
Figure 7. VL-BUS Ready Cycle with LBS16 Asserted Four-byte single cycle access is converted to two two-byte accesses.
AM79C965A
55
Initialization Block DMA Transfers
During execution of the PCnet-32 controller bus master initialization procedure, the PCnet-32 controller microcode will repeatedly request DMA transfers from the BIU. During each of these initialization block DMA transfers, the BIU will perform two data transfer cycles (eight bytes) and then it will relinquish the bus (see Figure 8). The two transfers within the mastership period will always be read cycles to ascending contiguous addresses. The two transfers in each initialization block DMA transfer will never be executed using linear burst mode. In 32-bit software mode, the number of bus mastership periods needed to complete the initialization procedure is 4. There are 7 double-words to transfer during the bus master initialization procedure, so four
bus mastership periods are needed in order to complete the initialization sequence. Note that the last double-word transfer of the last bus mastership period of the initialization sequence accesses an unneeded location. Data from this transfer is discarded internally. If a bus preemption event occurs during an initialization block DMA transfer, then the PCnet-32 controller will complete both of the two data transfer cycles of the initialization block DMA transfer before releasing the HOLD signal and relinquishing the bus. When SSIZE32 = 0 (CSR58[8]/BCR20[8]), then the number of bus mastership periods needed to complete the initialization procedure is 3 or 4.
Ti BCLK
T1
T2
T1
T2
Ti
Ti
Ti
Ti
Ti
Ti
ADS A4 A31, M/IO, D/C IADD i IADD i +4
W/R A2 A3, BE0 BE3 RDYRTN IADD i IADD i +4
BRDY
BLAST
To PCnet-32 To PCnet-32
D0 D31
18219-11
Figure 8. Initialization DMA Transfer
56
AM79C965A
Descriptor DMA Transfers
PCnet-32 controller will determine when a descriptor access is required. A descriptor DMA read will consist of two double-word transfers. A descriptor DMA write will consist of one or two double word transfer. The transfers within a descriptor DMA transfer mastership period will always be of the same type (either all read or all write). The transfers will be to addresses in the order as specified in Table 19 and Table 20 (note that MD indicates TMD or RMD). If buffer chaining is used (see Transmit and Receive Descriptor Table Entr y sections), writes to the descriptors that do not contain the End of Packet bit will consist of only one double-word. This write will be to the same location as the second of the two writes performed when the End of Frame has been processed (i.e. to the location that contains the descriptor OWNership bit, MD1[31]).
Descriptor DMA transfers will never be executed using linear burst mode. During read accesses, the byte enable signals will indicate that all byte lanes are active. Should some of the bytes not be needed, then the PCnet-32 controller will internally discard the extraneous information that was gathered during such a read. During write accesses, only the bytes which need to be written are enabled, by activating the corresponding byte enable pins. See Figure 9 and Figure 10. If a bus preemption event occurs during a descriptor DMA transfer, then the PCnet-32 controller will complete both of the two data transfer cycles of the descriptor DMA transfer, before releasing the HOLD signal and relinquishing the bus. The only significant differences between descriptor DMA transfers and initialization DMA transfers are that the addresses of the accesses follow different ordering.
Table 19. Bus Master Reads of Descriptors
16-Bit Software Mode Address SequenceA[7:0] 00 04 Bus Break LANCE Item Accessed MD1[15:0], MD0[15:0] MD3[15:0], MD2[15:0] PCnet-32 Item Accessed MD1[31:24], MD0[23:0] MD2[15:0], MD1[15:0] Address SequenceA[7:0]* 04 00 Bus Break 32-Bit Software Mode LANCE Item Accessed MD1[15:8], MD2[15:0] MD1[7:0], MD0[15:0] PCnet-32 Item Accessed MD1[31:0] MD0[31:0]
Table 20. Bus Master Writes of Descriptors
16-Bit Software Mode Address SequenceA[7:0] LANCE Item Accessed PCnet-32 Item Accessed MD2[15:0], MD1[15:0] MD1[31:24], MD0[23:0] Address SequenceA[7:0]* 32-Bit Software Mode LANCE Item Accessed PCnet-32 Item Accessed
04
MD3[15:0], MD2[15:0] MD1[15:0], MD0[15:0]
08
MD3[15:0], MD2[15:0] MD1[15:8], MD2[15:0]
MD2[31:0]
00
04
MD1[31:0]
Bus Break
Bus Break
* Address values for A[31:8] are constant throughout any single descriptor DMA transfer. Note that even though bits A{1:0] do not physically exist in the system, these bits must be set to ZERO in the descriptor base address.
AM79C965A
57
Ti BCLK
T1
T2
T1
T2
Ti
Ti
Ti
Ti
Ti
Ti
ADS A4 A31, M/IO, D/C MD1* MD0*
W/R A2 A3, BE0 BE3 RDYRTN MD1* MD0*
BRDY
BLAST
To PCnet-32 To PCnet-32
D0 D31
*Note that Message Descriptor addresses 1 and 0 are in descending order. 18219-12
Figure 9. Descriptor DMA Read
58
AM79C965A
Ti BCLK
T1
T2
T1
T2
Ti
Ti
Ti
Ti
Ti
Ti
ADS A4 A31, M/IO, D/C W/R A2 A3, BE0 BE3 RDYRTN MD2* MD1* MD2* MD1*
BRDY
BLAST
From PCnet-32 From PCnet-32
D0 D31
*Note that Message Descriptor addresses 2 and 1 are in descending order.
18219-13
Figure 10. Descriptor DMA Write
FIFO DMA Transfers
PCnet-32 controller microcode will determine when a FIFO DMA transfer is required. This transfer mode will be used for transfers of data to and from the PCnet-32 controller FIFOs. Once the PCnet-32 controller BIU has been granted bus mastership, it will perform a s e r i e s o f c o n s e c u t i ve t r a n s fe r c y c l e s b e fo r e relinquishing the bus. Each transfer will be performed sequentially, with the issue of an address, and the transfer of the corresponding data with appropriate output signals to indicate selection of the active data bytes during the transfer. All transfers within the master cycle will be either read or write cycles, and all transfers will be to contiguous, ascending addresses. The number of data transfer cycles contained within a single bus cycle is in general, dependent on the programming of the DMAPLUS option (CSR4, bit 14). Several other factors will also affect the length of the bus cycle period. The possibilities are as follows: If DMAPLUS = 0, a maximum of 16 transfers will be performed by default. This default value may be changed by writing to the burst register (CSR80). Note that DMAPLUS = 0 merely sets a maximum value. The
minimum number of transfers in the bus cycle will be determined by all of the following variables: the settings of the FIFO watermarks, the particular conditions existing within the FIFOs, receive and transmit status conditions, the value of the DMA Burst Cycle (CSR80), the value of the DMA Bus Activity Timer (CSR82), and the timing of any occurrence of preemption that takes place during the FIFO DMA transfer. If DMAPLUS = 1, the bus cycle will continue until the transmit FIFO is filled to its high threshold (read transfers) or the receive FIFO is emptied to its low threshold (write transfers), or until the DMA Bus Activity Timer value (CSR82) has expired. Other variables may also affect the end point of the burst in this mode. Among those variables are: the particular conditions existing within the FIFOs, receive and transmit status conditions, and bus preemption events. The FIFO thresholds are programmable (see description of CSR80), as are the Burst Cycle and Bus Activity Timer values. The exact number of transfer cycles in the case of DMAPLUS = 1 will be dependent on the latency of the system bus to the PCnet-32 controller's mastership request and the speed of bus operation, but
AM79C965A
59
will be limited by the value in the Bus Activity Timer register, the FIFO condition, receive and transmit status, and by preemption events, if any. Barring a timeout by either of these registers, or a bus preemption by another mastering device, or exceptional receive and transmit events, or an end of packet signal from the FIFO, the FIFO watermark settings and the extent of Bus Acknowledge latency will be the major factors determining the number of accesses performed during any given arbitration cycle when DMAPLUS = 1. The READY response of the memory device will also affect the number of transfers when DMAPLUS = 1, since the speed of the accesses will affect the state of the FIFO. (During accesses, the FIFO may be filling or emptying on the network end. A slower memory response will allow additional data to accumulate inside
of the FIFO (during write transfers from the receive FIFO). If the accesses are slow enough, a complete double word may become available before the end of the arbitration cycle and thereby increase the number of transfers in that cycle.) The general rule is that the longer the bus grant latency or the slower the bus transfer operations (or clock speed) or the higher the transmit watermark or the lower the receive watermark or any combination thereof the longer will be the average burst length. If a bus preemption event occurs during a FIFO DMA transfer, then the PCnet-32 controller will complete the current transfer and it will complete a maximum of four additional data transfer cycles before releasing the HOLD signal and relinquishing the bus.
Ti BCLK
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
Ti
ADS A4 A31, M/IO, D/C
W/R A2 A3, BE0 BE3 RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0 D31
18219-14
Figure 11. FIFO DMA Read
60
AM79C965A
Ti BCLK
T1
T2
T1
T2
T1
T2
T1
T2
T1
T2
Ti
ADS A4 A31, M/IO, D/C
W/R A2 A3, BE0 BE3 RDYRTN
BRDY
BLAST
From PCnet-32 From PCnet-32 From PCnet-32 From PCnet-32 From PCnet-32
D0 D31
18219-15
Figure 12. FIFO DMA Write
Note that A[1:0] do not exist in a 32-bit system, but both of these bits do exist in the buffer pointers that are passed to the PCnet-32 controller in the descriptor. A[1:0] values will be decoded and presented on the bus as byte enable (BE0-BE3) values during FIFO DMA transfers.
Linear Burst DMA Transfers
Once the PCnet-32 controller has been granted bus mastership, the PCnet-32 controller may request to perform linear burst cycles by de-asserting the BLAST signal. If the device being accessed wishes to support linear bursting, then it must assert BRDY and de-assert RDYRTN, with the same timing that RDYRTN would normally be provided. Linear bursting is only performed by the PCnet-32 controller if the BREADE and/or BWRITE bits of BCR18 are set. These bits individually enable/disable the ability of the PCnet-32 controller to perform linear burst accesses during master read operations and master write operations, respectively. Only FIFO data transfers will make use of the linear burst mode.
The first transfer in the linear burst will consist of both an address and a data cycle, but subsequent transfers will contain data only, until the LINBC upper limit of transfers have been executed. LINBC is a value from the BCR18 register. The linear burst "upper limit" is created by taking the BCR18 LINBC[2:0] value and multiplying by 4. The result is the number of transfers that will be performed within a single linear burst sequence. The entire address bus will still be driven with appropriate values during the data cycles. When the LINBC upper limit of data transfers have been performed, a new ADS may be asserted (if there is more data to be transferred), with a new address on the A2-A31 pins. Following the new ADS cycle, the linear bursting of data will resume. Ownership of the bus will be maintained until other variables cause the PCnet-32 controller to relinquish the bus. These variables have been discussed in the FIFO DMA transfers section above. They will be reviewed again within this section of the document.
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Transfers within a linear burst cycle will either be all read or all wr ite cycles, and will always be to contiguous ascending addresses. Linear Bursting of Read and Write operations can be individually enabled or disabled through the BREADE and BWRITE bits of BCR18 (bits 6 and 5). Linear Burst DMA transfers should be considered as a superset of the FIFO DMA transfers. Linear burst DMA transfers will only be used for data transfers to and from the PCnet-32 controller FIFOs and they will only be allowed when the burst enable bits of BCR18 have been set. Linear Read bursting and Linear Write bursting have individual enable bits in BCR18. Any combination of linear burst enable bit settings is permissible. Linear bursting is not allowed in systems that have BCLK frequencies above 33 MHz. Linear bursting is automatically disabled in VL-Bus systems that operate above this frequency by connecting the VLBEN pin to either ID(3) (for VL-Bus version 1.0 systems) or ID(4) AND ID(3) AND ID(1) AND ID(0) (for VL-Bus version 1.1 or 2.0 systems). In Am486-style systems that have BCLK frequencies above 33 MHz, disabling the linear burst capability is ideally carried out through EEPROM bit programming, since the EEPROM programming can be setup for a particular machine's architecture. All byte lanes are always considered to be active during all linear burst transfers. The BE3-BE0 signals will reflect this fact. Linear Burst DMA Starting Address Restrictions A PCnet-32 controller linear burst will begin only when the address of the current transfer meets the following condition: A[31:0] MOD (LINBC x 16) = 0, The following table illustrates all possible starting address values for all legal LINBC values. Note that
A[31:6] are don't care values for all addresses. Also note that while A[1:0] do not physically exist within a 32 bit system, they are valid bits within the buffer pointer field of descriptor word 0. Thus, where A[1:0] are listed, they refer to the lowest two bits of the descriptor's buffer pointer field. These bits will have an affect on determining when a PCnet-32 controller linear burst operation may legally begin and they will affect the output values of the BE3-BE0 pins, therefore they have been included in Table 21 as A[1:0]. It is not necessary for the software to insure that the buffer address pointer contained in descriptor word 0 matches the address restrictions given in the table. If the buffer pointer does not meet the conditions set forth in the table, then the PCnet-32 controller will simply postpone the start of linear bursting until enough ordinary FIFO DMA transfers have been performed to bring the current working buffer pointer value to a valid linear burst starting address. This operation is referred to as "aligning" the buffer address to a valid linear burst star ting address. Once this has been done, the PCnet-32 controller will recognize that the address for the current access is a valid linear burst starting address, and it will automatically begin to perform linear burst accesses at that time, provided of course that the software has enabled the linear burst mode. Note that if the software would provide only valid linear burst starting addresses in the buffer pointer, then the PCnet-32 controller could avoid performing the alignment operation. It would begin linear burst accesses on the very first of the buffer transfers thereby allowing a slight gain in bus bandwidth efficiency. Because of the linear burst starting address restrictions given in the table above, the PCnet-32 controller linear burst mode is completely compatible with the Am486style burst cycle when the LINBC[2:0] bits have been programmed with the value of 001.
Table 21. Linear Burst Addess
LINBC[2:0] LBS = Linear Burst Size (No. of Transfers) 0 (no linear bursting) 4 8 16 Reserved Linear Burst Addresses Beginning A[5:0] = (A[31:6] = Don't Care) Not Applicable 00, 10, 20, 30 00, 20 00 Not Applicable
0 1 2 4 3,5,6,7
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Linear Burst DMA Timing Diagram Explanatory Note Note that in all of the following timing diagrams for linear burst operations, a LINBC[2:0] value of 001 has been assumed. This translates to a linear burst length of four transfers. When the linear burst size is four transfers, then A[31:4] are stable within a single linear burst sequence, while A[3:2] and BE3-BE0 will change to reflect the address of the current transfer. Note that for larger values of LINBC[2:0] which correspond to longer linear burst lengths, the range of address pins that is stable during each burst sequence is smaller. For example, if LINBC[2:0] has the value of 010, then the linear burst length is eight double word transfers or 32 bytes of data. With this value of LINBC, it takes five address bits to track the changing addresses through the burst. This means that only A[31:5] are stable during each linear burst sequence, while A[4:2] and BE3-BE0 will change to reflect the address of the current transfer. For LINBC[2:0] = 100, only A[31:6] are stable during each linear burst sequence, while A[5:2] and BE3-BE0 will change to reflect the address of the current transfer, and so on. Table 22 summarizes this
information. Table 22. Stable Address Lines During Linear Burst
LINBC Value Portion of Address Bus Stable During Linear Burst Linear Bursting Disabled A[31:4] A[31:5] A[31:6]
Values of LINBC not shown in the table are not allowed. See the LINBC section of BCR18 for more details. Since all of the timing diagrams assume a LINBC[2:0] value of 001, then A[31:4] are shown to be stable within each linear burst sequence, and A[3:2] and BE3-BE0 are shown as changing in order to reflect the address of the current transfer. Linear Burst DMA Address Alignment Linear bursting may begin during a bus mastership period which was initially performing only ordinary DMA operations. (i.e. the value of BLAST is not restricted to ZERO for an entire bus mastership period if ZERO was the value of BLAST on the first access of a bus mastership period.) A change from non-linear bursting to linear bursting will normally occur during linear burst DMA address alignment operations. If the PCnet-32 controller is programmed for LINEAR burst mode (i.e. BREADE and/or BWRITE bits of BCR18 are set to ONE), and the PCnet-32 controller requests the bus, but the starting address of the first transaction does not meet the conditions as specified in the table above, then the PCnet-32 controller will perform burst-cycle accesses (i.e. it will provide an ADS for each transfer) until it arrives at an address that does meet the conditions described in the table. At that time, and without releasing the bus, the PCnet-32 controller will invoke the linear burst mode. The simple external manifestation of this event is that the value of the BLAST signal will change to de-asserted (driven high) on the next T2 cycle, thereby indicating a willingness of the PCnet-32 controller to perform linear bursting. (Note that burst-cycle accesses are performed with BLAST = 0.) Figure 13 shows an example of a linear burst DMA alignment operation being performed:
000 001 010 100
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Ti
Ti
T1
T2
T1
T2
T1
T2
T2
T2
T2
Ti
Ti
BCLK
ADS A4 A31, M/IO, D/C
W/R A2 A3, BE0 BE3 RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0 D31
HOLD
HLDA
18219-16
Figure 13. FIFO DMA Read Followed by Linear Burst Read During a Single Bus Mastership Period
Linear Burst DMA BLAST Signal Timing Linear burst cycles are requested by the PCnet-32 controller by de-asserting the BLAST signal (i.e. BLAST = 1). When BLAST is de-asserted by the PCnet-32 controller, the slave device is under no obligation to provide BRDY. Instead, it may provide RDYRTN in response to each of the PCnet-32 controller transfers. If RDYRTN is asserted during accesses in which the PCnet-32 controller has de-asserted BLAST, then the current transfer reverts to ordinary burst-cycle (see FIFO DMA Transfer section). When BLAST is asserted, it signals the end of the current linear burst sequence. In a cycle in which BLAST is asserted and following the assertion of either RDYRTN and/or BRDY by the slave device, the PCnet-32 controller may either relinquish the bus or it may initiate a new sequence of linear burst transfers without relinquishing the bus. If the PCnet-32 controller continues with a new sequence of linear burst transfers, the address asserted during the next T1 cycle will always be the next address in sequence from the previous T2 cycle. In other words, the PCnet-32 controller will never execute cycles within a single bus master-ship period that are not both ascending and contiguous, with the exception of the descriptor DMA accesses described above. The decision to continue bus ownership will depend upon several variables, including the state of the receive or transmit FIFO. All factors related to this decision are discussed later in this section. Figure 14 illustrates a typical case of multiple linear burst sequences being performed during a single bus mastership period.
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Ti BCLK
T1
T2
T2
T2
T2
T1
T2
T2
T2
T2
Ti
Ti
ADS A4 A31, M/IO, D/C
W/R A2 A3, BE0 BE3 RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0 D31
HOLD
HLDA
18219-17
Figure 14. Linear Burst Read
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Ti BCLK
Ti
T1
T2
T2
T2
T2
T2
T2
Ti
Ti
Ti
ADS A4 A31, M/IO, D/C
W/R A2 A3, BE0 BE3 RDYRTN
BRDY
BLAST
From PCnet-32 From PCnet-32 From PCnet-32 From PCnet-32
D0 D31
HOLD
HLDA
18219-18
Figure 15. Linear Burst Write with Wait States Added by the Slave Device on the Third Transfer
Linear Burst DMA Ready Wait States The PCnet-32 controller will insert wait states into linear burst DMA cycles if neither RDYRTN nor BRDY are sampled asserted at the end of each T2 cycle. Interrupted Linear Burst DMA Cycles The assertion of RDYRTN in the place of BRDY within a linear burst cycle will cause the linear burst to be "interrupted." In that case, the PCnet-32 controller will revert to ordinary two-cycle transfers that contain both a T1 and a T2 cycle, except that BLAST will remain de-asserted to show that linear bursting is still being requested by the PCnet-32 controller. This situation is defined as an interrupted linear burst cycle. If BRDY is sampled asserted (without also sampling RDYRTN asserted during the same access) during an interrupted linear 66 burst cycle in which BLAST is de-asserted, then linear bursting will resume. (Note that BLAST will become asserted during an interrupted linear burst cycle during the transfer that would have been the last transfer of the linear burst sequence, had the sequence not been interrupted.) When an interrupted linear burst cycle is resumed, then the next assertion of ADS will depend upon the initial starting point of the linear burst, rather than on the resumption point. For example, if the linear burst length = 4 (LINBC = 1), and BRDY is asserted during the first transfer, but RDYRTN is asserted on the second, then the PCnet-32 controller will revert to ordinary DMA transfers on the third transfer. If the responding device again asserts
AM79C965A
BRDY on the third access (while RDYRTN is deasserted), the PCnet-32 controller will resume linear bursting from the current address. It will produce 1 more data cycle before asserting the next ADS, i.e. PCnet-32 controller will keep track of the initial linear burst end point and will continue with the original linear burst after the RDYRTN interruption has occurred. Figure 16 illustrates an example of an interrupted linear burst. Note that BLAST is asserted in the fourth transfer after the initial linear burst began, even though the linear burst was interrupted with the assertion of RDYRTN and a new ADS was driven for the third t ra n s fe r. T h e ex t e r n a l e f fe c t o f t h e RDY RT N interruption is completely manifested in the insertion of the T1 cycle that contains the asserted ADS. The linear burst cycle is not affected in any other way. Partial Linear Burst Certain factors may cause the PCnet-32 controller to linearly burst fewer than the LINBC limit during a single linear burst sequence. BLAST will be asserted during the last data transfer. A linear burst that is terminated by BLAST before the LINBC limit is reached is called a partial linear burst.
A partial linear burst is recognizable in that the BLAST signal is asserted while fewer than the LINBC limit of transfers has been performed in the current linear burst sequence. Factors that could generate a partial linear burst include: s No more data available for transfers from the current transmit buffer s No more data available for transfer from the receive FIFO for this packet s No more space available for transfers to the current receive buffer If any of these conditions occurs, then the PCnet-32 controller will end the Linear Burst by asserting BLAST. Typically, during the case of a master read operation (for transmit buffer transfers), the last transfer in the linear burst sequence will be the last transfer executed before the PCnet-32 controller releases the bus. This is true of both par tial and completed linear burst sequences.
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Ti BCLK
Ti
T1
T2
T2
T1
T2
T2
T1
T2
T2
ADS A4-A31, M/IO, D/C
W/R A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
From PCnet-32 From PCnet-32 From PCnet-32 From PCnet-32 From PCnet-32
D0-D31
HOLD
HLDA
18219-19
Figure 16. "Interrupted" Linear Burst Write
Typically, during the case of a master write operation (for receive buffer transfers) when receive packet data has ended, the last transfer in the linear burst sequence will be the last transfer executed before the PCnet-32 controller releases the bus. This is true of both partial and completed linear burst sequences. However, if the next transfer that the PCnet-32 controller is scheduled to execute will be to the last available location of a receive or transmit buffer, then the PCnet-32 controller may assert BLAST on the current transfer and then use an ordinary cycle to make the last transfer to the buffer. This event occurs because of the restrictions placed upon the byte enable signals during the linear burst operation. As mentioned in the initial description of linear burst accesses (section Linear Burst DMA Transfers), all byte lanes of the data bus are always enabled during linear burst operations. Note,
however, that in the case of the last buffer location, the PCnet-32 controller may own only a portion of the double-word location. In such cases, it is necessary to discontinue linear burst accesses on the second from last buffer location so that an basic transfer with some byte lanes disabled can be used for the final transfer. Figure 17 shows a partial linear burst that occurred while approaching the transfer of the last bytes of data to a receive buffer. The linear burst begins when 10 bytes of space still remain in the receive buffer. (The number of spaces remaining for the figure as drawn could be anywhere from 9 to 12 spaces. The value of 10 spaces has been chosen just for purposes of illustration.) After the first linear burst transfer, the PCnet-32 controller sees that between 6 bytes of space remain, and knowing that the second transfer will use another 4 bytes of space, the PCnet-32 controller is
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able to predict that the third transfer will be the last. Therefore, it asserts BLAST on the second transfer to terminate the linear burst operation. However, the
PCnet-32 controller retains ownership of the bus so that it may, immediately thereon, make an basic transfer to the last two spaces in the buffer.
Ti BCLK
Ti
T1
T2
T2
T1
T2
Ti
Ti
Ti
ADS A4-A31, M/IO, D/C
W/R A2-A3, BE0-BE3 RDYRTN 100 104 108
BRDY
BLAST
From PCnet-32 From PCnet-32 From PCnet-32
D0-D31
HOLD
HLDA
18219-20
Figure 17. Typical Partial Linear Burst Write, Followed by a Basic Transfer During the Same Bus Mastership Period
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Length of Bus Mastership Period The number of data transfer cycles within the total bus mastership period is dependent on the programming of the DMAPLUS option (CSR4, bit 14). The possibilities are as follows: If DMAPLUS = 0, a maximum of 16 transfers will be performed by default. This default value may be changed by writing to the burst register (CSR80). Note that DMAPLUS = 0 merely sets a maximum value. The minimum number of transfers in the burst will be determined by all of the following variables: the settings of the FIFO watermarks and the conditions of the FIFOs, the value of the DMA Burst Cycle (CSR80), the value of the DMA Bus Activity Timer (CSR82), and any occurrence of preemption that takes place during the burst. If DMAPLUS = 1, linear bursting will continue until the transmit FIFO is filled to its high threshold or the receive FIFO is emptied to its low threshold, or until the DMA Bus Activity Timer value (CSR82) has expired. A bus preemption event is another cause of termination of cycles. The FIFO thresholds are programmable (see description of CSR80), as are the Burst Cycle and Bus Activity Timer values. The exact number of total transfer cycles in the case of DMAPLUS = 1 will be dependent on the latency of the system bus to the PCnet-32 controller's mastership request and the speed of bus operation, but will be limited by the value in the Bus Activity Timer Register, the FIFO condition and by preemption occurrences, if any. The exact response of the PCnet-32 controller to any of the conditions mentioned above can be complicated. For detail of the response to any particular stimulus, see each of the sections that describes PCnet-32 controller response. Note that the number of transfer cycles between each ADS assertion will always only be controlled by LINBC, RDYRTN, BOFF, HLDA and FIFO conditions. The number of transfer cycles separating ADS assertions will not be affected by DMAPLUS or by the values in the Burst Cycle and Bus Activity Timer Register. However, these factors can influence the number of transfers that is performed during any given arbitration cycle. Barring a time-out by the Burst Cycle or the Bus Activity Timer Register, or a bus preemption by another mastering device, the FIFO watermark settings and the extent of Bus Acknowledge latency will be the major factors in deter mining the number of accesses performed during any given arbitration cycle. The BRDY response time of the memory device will also affect the number of transfers, since the speed of the accesses will affect the state of the FIFO. (During accesses, the FIFO may be filling or emptying on the network end. For example, on a Receive operation, a slower device will allow additional data to accumulate inside of the FIFO. If the accesses are slow enough, a complete double word may become available before the end of the arbitration cycle and thereby increase the number of transfers in that cycle.) The general rule is that the longer the bus grant latency or the slower the bus transfer operations or the slower the clock speed or the higher the transmit watermark or the lower the receive watermark or any combination thereof, will produce longer total burst lengths. If a bus preemption event occurs after the execution of the first T2 cycle of the fourth from the last transfer cycle within a linear burst DMA sequence, then the PCnet-32 controller will complete the current linear burst sequence and will execute a new linear burst sequence before releasing the HOLD signal and relinquishing the bus. If a bus preemption event occurs before or concurrent with the execution of the first T2 cycle of the fourth from the last transfer cycle within a linear burst DMA sequence, then the PCnet-32 controller will complete the current linear burst sequence and then will release the HOLD signal and will relinquish the bus. Within the context of this explanation, a single transfer cycle refers to the execution of a data transfer, regardless of the number of clock cycles taken, i.e. wait states are included in this definition of a transfer cycle. See Figure 18.
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Ti BCLK ADS A4-A31, M/IO, D/C W/R A2-A3, BE0-BE3 RDYRTN
T1
T2
T2
T2
T2
Ti
Ti
Ti
Ti
Ti
Ti
T1
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0-D31
HOLD
*
HLDA
18219-21
*Note: Hold will always go inactive for 2 BLCK cycles before being reasserted. Figure 18. Linear Burst Read with Preemption During T2
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T1 BCLK
T1
T2
T2
T2
T2
T1
T2
T2
T2
T2
Ti
Ti
ADS A4-A31, M/IO, D/C W/R A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0-D31
HOLD
HLDA
18219-22
Figure 19. Linear Burst Read with Preemption During One of the Last Three T2 Cycles of the Sequence
If a bus preemption event occurs on a T1 cycle (specifically, a T1 cycle in which the ADS signal for a new linear burst sequence is asserted), then the next linear burst sequence will be executed before the PCnet-32 controller releases the HOLD signal and relinquishes
the bus. (If the T1 cycle in which the preemption occurred was to begin an basic transfer, then the basic transfer plus as many as two additional basic transfers will be executed before relinquishing the bus.)
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T2 BCLK
T2
T2
T2
T1
T2
T2
T2
T2
Ti
Ti
Ti
Ti
ADS A4 A31, M/IO, D/C
W/R A2 A3, BE0 BE3 RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0 D31
HOLD
*
HLDA
18219-23
*Note: HOLD is always held inactive for 2 BLCK cycles before being reasserted.
Figure 20. Linear Burst Read with Preemption that Occurs During the T1 Cycle
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Effect of B0FF Assertion of BOFF during a linear burst has two possible outcomes. In the case of BOFF asserted before the first BRDY (or RDYRTN) has been sampled, the PCnet-32 controller will restart the linear burst after the BOFF event has ended. A new ADS will be asserted with the original starting address for the halted linear burst. See Figure 21.
However, if the BOFF signal is asserted after the first BRDY (or RDYRTN) has been sampled, the PCnet-32 controller will revert to ordinary burst-cycle accesses following the BOFF event. In this case, the linear bursting will next occur when the memory address being accessed next meets the linear burst starting address requirements. If BOFF is sampled active on the same clock edge that BRDY or RDYRTN is sampled active, then the BOFF takes priority.
T1 BCLK
T1
T2
T2
Tb
Tb
T1b
T2
T2
T2
T2
T1
ADS A4-A31 M/IO D/C W/R A2, A3 BEO-BE3 RDYRTN
100
100
104
108
10C 110
BRDY BLAST D0-D31
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
HOLD HLDA
BOFF
18219-24
Figure 21. Restarted Linear Burst Read in which BOFF was Asserted Before BRDY of First Transfer in Linear Burst Sequency, Hence Linear Burst Sequence is Restarted When BOFF is De-asserted.
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T2 BCLK
T2
T2
Tb
Tb T1b
T2
T1
T2
T1
T2
T2
ADS A4 A31, M/IO, D/C W/R A2 A3, BE0 BE3 RDYRTN 100 104 108 108 10C 110 114
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0 D31
HOLD
HLDA
BOFF
18219-25
Figure 22. Restarted Linear Burst Read in which BOFF was Asserted After BRDY of First Transfer in Linear Burst Sequency. Hence, Linear Burst Reverts to Ordinary Cycles Until Next Legal Linear Burst Starting Address is Reached
In general, if the linear burst is suspended by another bus master (either because of BOFF or PCnet-32 controller releasing HOLD) then any partially completed linear burst access will not resume when the PCnet-32 controller regains bus ownership. But if the PCnet-32 controller linear burst is interrupted by the receipt of
RDYRTN in place of BRDY, then the PCnet-32 controller will resume the linear burst operation as indicated by the BLAST signal. Register accesses cannot be perfor med to the PCnet-32 device while BOFF is asserted.
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Effect of AHOLD Assertion of AHOLD during Linear Burst transfers will cause the PCnet-32 controller to float some portion of the address bus beginning at the next clock cycle. If BRDY is returned while AHOLD is active, then the linear burst sequence will continue until the current burst would otherwise normally terminate, since the data bus and the lower portion of the address bus may remain active during AHOLD. However, a new linear burst sequence, requiring a new ADS assertion, will not be started while AHOLD is active. When AHOLD is asserted during T1 of a linear burst, then the linear burst operation will be suspended until AHOLD is de-asserted. Once AHOLD is de-asserted, then the PCnet-32 controller will start the suspended linear burst with the intended address. See Figure 23. (Note that the intended T1 of the linear burst sequence has been labeled Ta in the figure, since a T1 was never executed due to the suspension of the address bus required by the assertion of AHOLD.) When AHOLD is asserted in the middle of a linear burst, the linear burst may proceed without stalling or halting. AHOLD requires that PCnet-32 controller float a portion of its address bus, but linear burst data cycles will still proceed, since the AHOLD signal only affects a portion of the address bus, and that portion of the address bus is not being used for the middle accesses of a linear burst. However, if AHOLD is asserted in the middle of a linear burst operation, and the AHOLD signal is held long enough that a new linear burst sequence will start (a new ADS is to be issued by the PCnet-32 controller) then at the end of the current linear sequence, the PCnet-32 controller must wait for the AHOLD signal to become inactive before beginning the next linear sequence, since the AHOLD signal would now interfere with the PCnet-32 controller's wish to assert ADS and a new address on the entire address bus. During the time that the PCnet-32 controller is waiting for the release of the AHOLD signal, the PCnet-32 controller will
continue to drive the command signals, but ADS will be
driven inactive. Note that if RDYRTN is asserted during a linear burst sequence while AHOLD is active, then no more access will be performed until AHOLD is de-asserted. This is because the assertion of RDYRTN will cause the PCnet-32 controller to insert a new T1 cycle into the linear burst. A T1 cycle requires assertion of ADS, but ADS assertion is not allowed as long as AHOLD is still asserted. Therefore, the T1 cycle is delayed until the AHOLD is de-asserted. The portion of the Address Bus that will be floated at the time of an address hold operation will be determined by the value of the Cache Line Length register (BCR18, bits 15-11). Table 23 lists all of the legal values of CLL showing the portion of the Address Bus that will become floated during an address hold operation.
Table 23. CLL Value of Floated Address in AHOLD
CLL Value Floated Portion of Address Bus During AHOLD None A31-A2 A31-A3 Reserved CLL Value A31-A4 Reserved CLL Values A31-A5 Reserved CLL Values A31-A6 Reserved CLL Values
00000 00001 00010 00011 00100 00101-00111 01000 01001-01111 10000 10001-11111
Note that the default value of CLL after H_RESET is 00100. All timing diagrams in this document are drawn with the assumption that this is the value of CLL.
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T1
T1
T1
Ta
Ta
Ta
T1
T2
T2
T2
T2
T1
BLCK ADS
A4-A31 M/IO, D/C W/R A2-A3, BEO-BE3 RDYRTN BRDY BLAST D0-D31
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
valid
100
104
108
10C 110
HOLD HLDA AHOLD
18219-26
Figure 23. Linear Burst Read in which AHOLD was Asserted During T1 in the Linear Burst Sequence; Linear Burst Sequence is Started when AHOLD is De-asserted
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Ti BCLK
Ti
T1
T2
T2
T2
T2
Th
Th
T1
T2
T2
ADS A4-A31 M/IO, D/C W/R A2-A3, BE0 - BE3 RDYRTN 100 104 108 10C 110 114 100 110
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
D0-D31
AHOLD
HOLD
HLDA
18219-27
Figure 24. Linear Burst Read Cycle with AHOLD
Note that Linear Burst sequence is allowed to complete in spite of AHOLD, but next linear Burst sequence is prevented from beginning until AHOLD is de-asserted. Note that if the BRDY (or RDYRTN) signal is not returned while AHOLD is active, then the PCnet-32 controller will resume driving the same address onto the address bus when AHOLD is released. The PCnet-32 controller will not reissue the ADS signal at this time. Bus Activity Timer Register Time Out During Linear Burst When the Bus Activity Timer Register (CSR82 bits [15:0]) times out before or concurrent with the execution of the first T2 cycle of the fourth from the last transfer cycle within a linear burst DMA sequence, then the linear burst will continue until a legal starting
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address is reached, and then the PCnet-32 controller will relinquish the bus. If the Bus Activity Timer Register times out after the execution of the first T2 cycle of the fourth from the last transfer cycle within a linear burst DMA sequence, then the PCnet-32 controller will complete the current linear burst sequence and will execute a new linear burst sequence before releasing the HOLD signal and relinquishing the bus. (Effectively, the Bus Activity Timer time-out is treated in a manner identical to the occurrence of a preemption event.) Therefore, when programmed for Linear Burst mode, the PCnet-32 controller bus mastership time may exceed the Bus Activity Timer limit. This is done because an immediate abort of the linear burst due to timer expiration would leave the current buffer pointer at an unaligned location. This would cause an address alignment of several ordinary cycles to be executed during the next FIFO DMA operation. Repeated occurrences of this nature would compromise the usefulness of the linear burst mode, since this would increase the number of non-linear burst cycles that are performed. This in turn would increase the bus bandwidth requirement of the PCnet-32 controller. Therefore, because the PCnet-32 controller Linear Burst operation does not strictly obey the Burst Timer, the user should program the Burst Timer value in such a manner as to include the expected linear burst release time. If the user has enabled the Linear Burst function, and wishes the PCnet-32 controller to limit bus activity to MAX_TIME ms, then the Burst Timer should be programmed to a value of: MAX_TIME- [((3+lbs) x w + 10 + lbs) x (BCLK period)] This is because the PCnet-32 controller may use as much as one "linear burst size" plus three transfers in order to complete the linear burst before releasing the bus. As an example, if the linear burst size is 4 transfers, and the number of wait states for the system memory is 2, and the BCLK period is 30 ns and the MAX time allowed on the bus is 3 ms, then the Burst Timer should be programmed for: MAX_TIME- [((3+lbs) x w + 10 + lbs) x (BCLK period)]; 3 ms - [(3 + 4) x 2 +10 + 4) x (30 ns)] = 3 ms - (28 x 30 ns) = 3 - 0.84 ms = 2.16 ms. Then, if the PCnet-32 controller's Burst Timer times out after 2.16 ms when the PCnet-32 controller has completed all but the last three transfers of a linear burst, then the PCnet-32 controller may take as much as 0.84 ms to complete the bursts and release the bus. The bus release will occur at 2.16 + 0.84 = 3 ms.
Burst Cycle Time Out During Linear Burst When the Burst Cycle (CSR80 bits [7:0]) times out in the middle of a linear burst, the linear burst will continue until a legal starting address is reached, and then the PCnet-32 controller will relinquish the bus. The discussion for the Burst Cycle is identical to the discussion for the Bus Activity Timer Register, except that the quantities are in terms of transfers instead of in terms of time. The equation for the proper burst register setting is: Burst count setting = (desired_max DIV (length of linear burst in transfers)) x length of linear burst in transfers, where DIV is the operation that yields the INTEGER portion of the operation. Illegal Combinations of Watermark and LINBC Certain combinations of watermark programming and LINBC programming may create situations where no linear bursting is possible, or where the FIFO may be excessively read or excessively written. Such combinations are declared as illegal. Combinations of watermark settings and LINBC settings must obey the following relationship: watermark (in bytes) S LINBC (in bytes) Combinations of watermark and LINBC settings that violate this rule may cause unexpected behavior. Slave Timing Slave timing in the PCnet-32 controller is designed to perform to both Am486 32-bit timing requirements and VESA VL-Bus timing requirements at the same time. Since the VESA VL-Bus is based upon Am486 bus timing, there is really little difference evident, except for hold-off requirements on the part of the slave driving the RDY, BRDY, and data signals when the high speed write signal is false. VESA VL-Bus requires that none of these signals are driven by the slave until the second T2 cycle when the high speed write signal is false. Since the PCnet-32 controller does not examine the high-speed write bit, it assumes that this signal is never true, and therefore always obeys the more stringent requirement of not being allowed to drive RDY, BRDY and the data bus until the second T2. In addition, the PCnet-32 controller will drive RDY and BRDY inactive for one half BCLK cycle at the end of the slave access, immediately following the BCLK cycle in which the PCnet-32 controller asserted RDY. Again, this behavior is required by the VESA VL-Bus specification, but it is not required for operation within an Am486 system. The PCnet-32 controller performs in this manner, regardless of the PCnet-32 controller mode setting. Slave timing can generally be inferred from the bus master timing diagrams, with the exception of the following information:
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PCnet-32 controller never responds with BRDY active during slave accesses. All PCnet-32 controller slave responses use only the RDY signal. BRDY will always be de-asserted during all PCnet-32 controller slave accesses. RDY is a PCnet-32 controller output signal. It is used during PCnet-32 controller slave accesses. RDYRTN is a PCnet-32 controller input signal. It is used during all PCnet-32 controller bus master accesses, as well as during PCnet-32 controller slave read accesses. The typical number of wait states added to a slave access on the part of the PCnet-32 controller is 6 or 7 BCLK cycles, depending upon the relative phases of the internal Buffer Management Unit clock and the BCLK signal, since the internal Buffer Management Unit clock is a divide-by-two version of the BCLK signal. The PCnet-32 controller RDY and RDYRTN signals may be wired together. This allows the PCnet-32
controller to operate within a system that has a single READY signal. The LDEV signal is generated in response to a valid PCnet-32 controller I/O address on the bus together with a valid ADS signal. LDEV is generated in an asynchronous manner by the PCnet-32 controller. See the parameter listings for delay values of the LDEV signal. RDY, BRDY and D[31:0] are never driven until the second T2 state of a slave access. Before that time, it is expected that a system pull-up device is holding the RDY and BRDY signals in a de-asserted state. The RDY and BRDY signals are always driven high for one half BCLK cycle immediately following the BCLK period during which RDY was driven asserted. Then the RDY and BRDY signals are floated. This behavior is performed regardless of the PCnet-32 controller mode setting. See Figure 25.
Ti BCLK
T1
T2
T2
T2
T2
T2
T2
T2
T2x
Ti
ADS ADDRESS, BE0-BE3, M/IO, D/C W/R
Valid
Not Valid
RDY
BRDY
RDYRTN
LDEV
From PCnet-32
D0-D31
Not Valid
18219-28
Figure 25. Slave RDY Timing
VESA VL-Bus Mode Timing VESA VL-Bus mode functional timing is essentially identical to the timing of the Am486 32-bit mode, except that the bus request and bus acknowledge signals have inverted senses from those shown in the previous timing diagrams and the AHOLD signal does not exist while the PCnet-32 controller is programmed
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for VL-Bus mode. In addition, dynamic bus sizing is supported in VESA VL-Bus mode, through the use of the LBS16 signal. The following section describes possible LBS16 interactions while programmed for the VESA VL-Bus mode of operation. Other differences exist between VL-Bus mode and Am486 mode, but these other differences are not directly related to the master or slave cycle timings. Effect of LBS16 (VL-Bus mode only) Dynamic bus sizing is recognized by the PCnet-32 controller while operating in the VL-Bus mode. The LBS16
signal is used to indicate to the PCnet-32 controller whether the VL-Bus target is a 16-bit or 32-bit peripheral. When the target device indicates that it is 16 bits in width by asserting the LBS16 signal at least one LCLK period before asserting the BRDY signal, then the PCnet-32 controller will dynamically respond to the size constraints of the peripheral by performing additional accesses. Table 24 indicates the sequence of accesses that will be performed by the PCnet-32 controller in response to the assertion of LBS16.
Table 24. Data Transfer Sequence from 32-Bit Wide to 16-Bit Wide
Current Access BE3 1 1 1 0 1 1 0 1 0 0 BE2 1 1 0 0 1 0 0 0 0 1 BE1 1 0 0 0 0 0 0 1 1 1 BE0 0 0 0 0 1 1 1 1 1 1 BE3 NR* NR* 1 0 NR* 1 0 NR* NR* NR* 0 0 1 1 1 1 0 0 1 1 1 1 Next with LBS16 BE2 BE1 BE0
*NR = No second access Required for these cases.
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Figure 26 shows an example of an exchange between a 16-bit VL-Bus peripheral and the PCnet-32 controller during ordinary read cycles while programmed for VLBus mode of operation. Note that the LBS16 signal is asserted during the LCLK that precedes the assertion of RDYRTN. In this particular case, in order to maintain zero-wait state accesses, the 16-bit target must generate LBS16 in a very short time in order to meet the required setup time of LBS16 into the PCnet-32 controller. If the peripheral were incapable of meeting the required setup time, then a wait state would be needed in order to insure that LBS16 is asserted at
least one LCLK prior to the assertion of the RDYRTN signal. This situation is illustrated in the second double word access of the diagram. The wait state only needs to be inserted on the first access of the sequence, since from that point on, LBS16 could be held active low until the entire double word transfer had completed, thus adequately satisfying the LBS16 setup requirement for the second RDYRTN assertion. Note that only two bytes of data are transferred during each T2 cycle so that the total number of bytes transferred during each access is four.
Ti LCLK
Ti
T1
T2
T2
T1
T2
T2
T2
Ti
Ti
ADS ADR4 ADR31, M/IO, D/C 100 104
W/R ADR2 ADR3, BE2 BE3 BE0 BE1 100 104
104
RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
DAT0 DAT31
LBS16
LREQ
LGNT
18219-29
Figure 26. VL-Bus Basic Read with LBS16
Figure 27 shows an example of an exchange between a 16-bit VL-Bus peripheral and the PCnet-32 controller
during linear burst mode while programmed for VL-Bus mode of operation. Note that the LBS16 signal is as-
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serted during the LCLK that precedes the assertion of BRDY. In this particular case, in order to maintain zerowait state accesses, the 16-bit target must generate LBS16 in a very short time in order to meet the required setup time of LBS16 into the PCnet-32 controller. If the peripheral were incapable of meeting the required setup time, then a wait state would be needed in order to insure that LBS16 is asserted at least one LCLK prior to the assertion of the BRDY signal. For linear burst sequences, this wait state would only need to be inserted on the first access of the sequence, since from that point on, LBS16 could be held active low until the entire sequence had completed, thus adequately
satisfying the LBS16 setup requirement for each subsequent BRDY assertion. Note that only 2 bytes of data are transferred during each T2 cycle so that the total number of bytes transferred during the linear burst sequence is 16, even though 8 T2 cycles are executed. When the assertion of LBS16 during a PCnet-32 controller master access has created the need for a second access as specified in the table above, and the WBACK signal becomes active during the second access, then when WBACK is de-asser ted, the PCnet-32 controller will repeat both accesses of the pair.
Ti LCLK
Ti
T1
T2
T2
T2
T2
T2
T2
T2
T2
Ti
Ti
ADS ADR4- ADR31, M/IO, D/C W/R ADR2- ADR3, BE2 -BE3 BE0-BE1
100
100
104
108
10C
100
RDYRTN
BRDY
BLAST
To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32 To PCnet-32
DAT0- DAT31 LBS16
LREQ
LGNT
18219-30
Figure 27. VL-Bus Linear Burst Read with LBS16
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Bus Master and Bus Slave Data Byte Placement The general rule of data placement is that the active data byte lanes are indicated by the byte enable signals for all transfers. Note that during all master read operations, the PCnet-32 controller will always activate all byte enables, even though some byte lanes may not contain "valid" data as indicated by a buffer pointer value. In such instances, the PCnet-32 controller will internally discard unneeded bytes. Note that in all 32-bit environments, regardless of the mode settings, the placement of data bytes on the data bus during all PCnet-32 controller bus operations (master and slave) will proceed in accordance with the data byte duplication rules of the Am386DX. The Am386DX requirement is for duplication of active data bytes in corresponding lower-half byte lanes when the access is a byte or word access that utilizes the upper half of the data bus. PCnet-32 controller performs data byte duplication in this manner. The Am386DX does not indicate byte duplication when the active data bytes of a byte or word access are exclusively contained in the lower half of the data bus, therefore, the PCnet-32 controller will not perform data byte duplication in this
case. Byte duplication for bus master writes and bus slave reads will follow Table 25. A[1:0] in the table refer to software pointers, since A[1:0] pins do not physically exist in the system. (Software pointers include I/O address software pointers in the driver code for I/O accesses to the PCnet-32 controller, or software pointers for the initialization block, descriptor areas or buffer areas that are used by the PCnet-32 controller during master accesses.) For master read operations, the PCnet-32 controller expects data according to the byte enable signaling only. Byte lanes with inactive byte enables are expected to carry invalid data. For slave write operations, the PCnet-32 controller expects data according to the byte enable signaling only. Byte lanes with inactive byte enables are expected to carry invalid data. For master write operations, the PCnet-32 controller will produce data as indicated in Table 25. For slave read operations, the PCnet-32 controller will produce data as indicated for the BSWP = 0 cases in Table 25, regardless of the actual setting of the BSWP bit.
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Table 25. Master and Slave Byte Placement
Case No. 1a 1b 2b 3a 3b 4a 4b 5a 5b 6a 6b 7a 7b 8a 8b 9a 9b 10a 10b 11a 11b 12a 12b 13a 13b 14a 14b 15a 15b 16a 16b A[1:0] 00 00 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 00 00 01 01 10 10 11 11 BSWP 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BE3-BE0 0000 0000 1000 0011 1100 0111 1110 1000 0001 0001 1000 0011 1100 0111 1110 1100 0011 1001 1001 0011 1100 0111 1110 1110 0111 1101 1011 1011 1101 0111 1110 D[31:24] Byte3 Byte0 Undef Byte1 Undef Byte0 Undef Undef Byte0 Byte2 Undef Byte1 Undef Byte0 Undef Undef Byte0 Undef Undef Byte1 Undef Byte0 Undef Undef Byte0 Undef Undef Undef Undef Byte0 Undef D[23:16] Byte2 Byte1 Byte0 Byte0 Undef Undef Undef Byte2 Byte1 Byte1 Byte0 Byte0 Undef Undef Undef Undef Byte1 Byte1 Byte0 Byte0 Undef Undef Undef Undef Undef Undef Byte0 Byte0 Undef Undef Undef D[15:8] Byte1 Byte2 Byte1 Copy1 Byte0 Copy0 Undef Byte1 Byte2 Byte0 Byte1 Copy1 Byte0 Copy0 Undef Byte1 Copy0 Byte0 Byte1 Copy1 Byte0 Copy0 Undef Undef Copy0 Byte0 Undef Undef Byte0 Copy0 Undef D[7:0] Byte0 Byte3 Byte2 Copy0 Byte1 Undef Byte0 Byte0 Undef Undef Byte2 Copy0 Byte1 Undef Byte0 Byte0 Copy1 Undef Undef Copy0 Byte1 Undef Byte0 Byte0 Undef Undef Copy0 Copy0 Undef Undef Byte0
Note that cases 10, 12, and 15 will not normally be produced during PCnet-32 controller bus master operations. These cases will only occur during bus master operations if the software programs an extremely short buffer size into the descriptor BCNT
field, where extremely short means exactly 4, 3, 2 or 1 bytes in length. BSWP = 0 corresponds to little Endian byte ordering. BSWP = 1 corresponds to big Endian byte ordering.
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Buffer Management Unit
The buffer management unit is a micro-coded state machine which implements the initialization procedure and manages the descriptors and buffers. The buffer management unit operates at a speed of BCLK 2. Initialization PCnet-32 controller initialization includes the reading of the initialization block in memor y to obtain the operating parameters. The initialization block must be located on a double word (4-byte) address boundary, regardless of the setting of the SSIZE32, (CSR58[8]/ BCR20[8]) bit. The initialization block is read when the INIT bit in CSR0 is set. The INIT bit should be set before or concurrent with the STRT bit to insure correct operation. Two double-words are read during each per iod of bus mastership. When SSIZE32 = 1 (CSR58[8]/ BCR20[8]), this results in a total of 4 arbitration cycles (3 arbitration cycles if SSIZE32 = 0). Once the initialization block has been completely read in and internal registers have been updated, IDON will be set in CSR0, and an interrupt generated (if IENA is set). At this point, the BMU knows where the receive and transmit descriptor rings and hence, normal network operations will begin. The Initialization Block is vectored by the contents of CSR1 (least significant 16 bits of address) and CSR2 (most significant 16 bits of address). The block contains the user defined conditions for PCnet-32 controller operation, together with the base addresses and length information of the transmit and receive descriptor rings. There is an alternative method to initialize the PCnet-32 controller. Instead of initialization via the initialization block in memory, data can be written directly into the appropriate registers. Either method may be used at the discretion of the programmer. If the registers are written to directly, the INIT bit must not be set, or the initialization block will be read in, thus overwriting the previously written information. Please refer to Appendix C for details on this alternative method. Re-Initialization The transmitter and receiver sections of the PCnet-32 controller can be turned on via the initialization block (MODE Register DTX, DRX bits; CSR15[1:0]). The states of the transmitter and receiver are monitored by the host through CSR0 (RXON, TXON bits). The PCnet-32 controller should be reinitialized if the transmitter and/or the receiver were not turned on during the original initialization, and it was subsequently required to activate them or if either section was shut off due to the detection of an error condition (MER, UFLO, TX BUFF error).
Re-initialization may be done via the initialization block or by setting the STOP bit in CSR0, followed by writing to CSR15, and then setting the START bit in CSR0. Note that this form of restart will not perform the same in the PCnet-32 controller as in the LANCE. In par ticular, upon restar t, the PCnet-32 controller reloads the transmit and receive descriptor pointers with their respective base addresses. This means that the software must clear the descriptor own bits and reset its descriptor ring pointers before the restart of the PCnet-32 controller. The reload of descriptor base addresses is performed in the LANCE only after initialization, so a restar t of the LANCE without initialization leaves the LANCE pointing at the same descriptor locations as before the restart. Buffer Management Buffer management is accomplished through message descriptor entries organized as ring structures in memory. There are two rings, a receive ring and a transmit ring. The size of a message descriptor entry is 4 double-words, or 16 bytes, when SSIZE32 = 1. The size of a message descriptor entry is 4 words, or 8 bytes, when SSIZE32 = 0 (CSR58[8]/BCR20[8]). Descriptor Rings Each descriptor ring must be organized in a contiguous area of memory. At initialization time (setting the INIT bit in CSR0), the PCnet-32 controller reads the userdefined base address for the transmit and receive descriptor rings, as well as the number of entries contained in the descriptor rings. Descriptor ring base addresses must be on a 16-byte boundary when SSIZE32 = 1, or on an 8-byte boundary when SSIZE32 = 0. A maximum of 128 (or 512, depending upon the value of SSIZE32) ring entries is allowed when the ring length is set through the TLEN and RLEN fields of the initialization block. However, the ring lengths can be set beyond this range (up to 65535) by writing the transmit and receive ring length registers (CSR76, CSR78) directly. Each ring entry contains the following information: 1. The address of the actual message data buffer in user or host memory 2. The length of the message buffer 3. Status information indicating the condition of the buffer To permit the queuing and dequeuing of message buffers, ownership of each buffer is allocated to either the PCnet-32 controller or the host. The OWN bit within the descriptor status information, either TMD or RMD (see section on TMD or RMD), is used for this purpose. OWN = "1" signifies that the PCnet-32 controller currently has ownership of this ring descriptor and its associated buffer. Only the owner is permitted to relinquish ownership or to write to any field in the
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descriptor entry. A device that is not the current owner of a descriptor entry cannot assume ownership or change any field in the entry. A device may, however, read from a descriptor that it does not currently own. Software should always read descriptor entries in sequential order. When software finds that the current descriptor is owned by the PCnet-32 controller, then the software must not read "ahead" to the next descriptor. The software should wait at the unOWNed descriptor until ownership has been granted to the software (when SPRINTEN = 1 (CSR3, bit5), then this rule is modified. See the SPRINTEN description). Strict adherence to these rules insures that "Deadly Embrace" conditions are avoided. Descriptor Ring Access Mechanism At initialization, the PCnet-32 controller reads the base address of both the transmit and receive descriptor
rings into CSRs for use by the PCnet-32 controller during subsequent operations. As the final step in the self-initialization process, the base address of each ring is loaded into each of the current descriptor address registers and the address of the next descriptor entry in the transmit and receive rings is computed and loaded into each of the next descriptor address registers. When SSIZE32 = 0, software data structures are 16 bits wide. Figure 28 illustrates the relationship between the Initialization Base Address, the Initialization Block, the Receive and Transmit Descriptor Ring Base Addresses, the Receive and Transmit Descriptors and the Receive and Transmit Data Buffers, for the case of SSIZE32 = 0.
N
N
N
N

24-Bit Base Address Pointer to Initialization Block CSR2
RES IADR[23:16]
Rcv Descriptor Ring
1st Desc. Start 2nd Desc. Start
CSR1
IADR[15:0]
RMD0 RMD1 RMD2
RMD0 RMD3
Initialization Block
MODE PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN TLEN RES RDRA[23:16] TDRA[15:0] RES TDRA[23:16]
Rcv Buffers
Data Buffer 1
Data Buffer 2
Data Buffer N

M
M
M
M
RX DESCRIPTOR RINGS

Xmt Descriptor
RX DESCRIPTOR RINGS Ring 1st Desc. Start 2nd Desc. Start
TMD0 TMD1 TMD2
TMD0 TMD3
Xmt Buffers
Data Buffer 1
Data Buffer 2
Data Buffer M

18219-35
Figure 28. 16-Bit Initialization Block Descriptor Rings
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When SSIZE32 = 1, software data structures are 32 bits wide. Figure 29 illustrates the relationship between the Initialization Base Address, the Initialization Block, the Receive and Transmit Descriptor Ring Base Addresses (TDRA/RDRA), the Receive and Transmit Descriptors and the Receive and Transmit Data Buffers, for the case of SSIZE32 = 1. Polling If there is no network channel activity and there is no pre- or post-receive or pre- or post-transmit activity being performed by the PCnet-32 controller, then the PCnet-32 controller will periodically poll the current receive and transmit descriptor entries in order to ascertain their ownership. If the DPOLL bit in CSR4 is set, then transmit polling function is disabled.
A typical polling operation consists of the following: The PCnet-32 controller will use the current receive descriptor address stored internally to vector to the appropriate Receive Descriptor Table Entry (RDTE). It will then use the current transmit descriptor address (stored internally) to vector to the appropriate Transmit Descriptor Table Entry (TDTE). The accesses will be made in the following order: RMD1, then RMD0 of the current RDTE during one bus arbitration, and after that, TMD1, then TMD0 of the current TDTE during a second bus arbitration. All information collected during polling activity will be stored inter nally in the appropriate CSRs (i.e. CSR18, CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52). UnOWNed descriptor status will be internally ignored.
N
N
N
N

32-Bit Base Address Pointer to Initialization Block CSR2
IADR[31:16]
Rcv Descriptor Ring
1st Desc. Start 2nd Desc. Start
CSR1
IADR[15:0]
RMD0 RMD1 RMD2
RMD0 RMD3
Initialization Block
TLEN RES RLEN RES MODE PADR[31:0] PADR[47:32] RES LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0]
Rcv Buffers
Data Buffer 1
Data Buffer 2
Data Buffer N

M
M
M
M
RX DESCRIPTOR RINGS

Xmt Descriptor
RX DESCRIPTOR RINGS Ring 1st Desc. Start 2nd Desc. Start
TMD0 TMD1 TMD2
TMD0 TMD3
Xmt Buffers
Data Buffer 1
Data Buffer 2
Data Buffer M
Figure 29. 32-Bit Initialization Block and Descriptor Ring A typical receive poll is the product of the following conditions: 1. PCnet-32 controller does not possess ownership of the current RDTE and the poll time has elapsed and RXON = 1, or

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2. PCnet-32 controller does not possess ownership of the next RDTE the poll time has elapsed and RXON = 1. If RXON = 0 the PCnet-32 controller will never poll RDTE locations. The ideal system should always have at least one RDTE available for the possibility of an unpredictable receive event. (This condition is not a requirement. If this condition is not met, it simply means that frames will be missed by the system because there was no buffer space available.) But the typical system usually has at least one or two RDTEs available for the possibility of an unpredictable receive event. Given that this condition is satisfied, the current and next RDTE polls are rarely seen and hence, the typical poll operation simply consists of a check of the status of the current TDTE. When there is only one RDTE (because the RLEN was set to zero), then there is no "next RDTE" and ownership of "next RDTE" cannot be checked. If there is at least one RDTE, the RDTE poll will rarely be seen and the typical poll operation simply consists of a check of the current TDTE. A typical transmit poll is the product of the following conditions: 1. PCnet-32 controller does not possess ownership of the current TDTE and DPOLL = 0 and TXON = 1 and the poll time has elapsed, or 2. PCnet-32 controller does not possess ownership of the current TDTE and DPOLL = 0 and TXON = 1 and a frame has just been received, or 3. PCnet-32 controller does not possess ownership of the current TDTE and DPOLL = 0 and TXON = 1 and a frame has just been transmitted. Setting the TDMD bit of CSR0 will cause the microcode c o n tr o l l e r t o ex i t t h e p o l l c o u nt i n g c o de a n d immediately perform a polling operation. If RDTE ownership has not been previously established, then an RDTE poll will be performed ahead of the TDTE poll. If the microcode is not executing the poll counting code when the TDMD bit is set, then the demanded poll of the TDTE will be delayed until the microcode returns to the poll counting code. The user may change the poll time value from the default of 65,536 BCLK periods by modifying the value in the Polling Interval register (CSR47). Note that if a nondefault value is desired, then a strict sequence of setting the INIT bit in CSR0, waiting for IDON (CSR0[8]), then writing to CSR47, and then setting
STRT in CSR0 must be observed, otherwise the default value will not be overwritten. See the CSR47 section for details. Transmit Descriptor Table Entry (TDTE) If, after a TDTE access, the PCnet-32 controller finds that the OWN bit of that TDTE is not set, then the PCnet-32 controller resumes the poll time count and reexamines the same TDTE at the next expiration of the poll time count. If the OWN bit of the TDTE is set, but STP = 0, the PCnet-32 controller will immediately request the bus in order to reset the OWN bit of this descriptor. (This condition would normally be found following a LCOL or RETRY error that occurred in the middle of a transmit frame chain of buffers.) After resetting the OWN bit of this descriptor, the PCnet-32 controller will again immediately request the bus in order to access the next TDTE location in the ring. If the OWN bit is set and the buffer length is 0, the OWN bit will be reset. In the LANCE the buffer length of 0 is interpreted as a 4096-byte buffer. It is acceptable to have a 0 length buffer on transmit with STP = 1 or STP = 1 and ENP = 1. It is not acceptable to have 0 length buffer with STP = 0 and ENP =1. If the OWN bit is set and the start of packet (STP) bit is set, then microcode control proceeds to a routine that will enable transmit data transfers to the FIFO. The PCnet-32 controller will look ahead to the next transmit descriptor after it has performed at least one transmit data transfer from the first buffer. (More than one transmit data transfer may possibly take place, depending upon the state of the transmitter.) The contents of TMD0 and TMD1 will be stored in Next Xmt Buffer Address (CSR64 and CSR65), Next Xmt Byte Count (CSR66) and Next Xmt Status (CSR67) regardless of the state of the OWN bit. This transmit descriptor lookahead operation is performed only once. If the PCnet-32 controller does not own the next TDTE (i.e. the second TDTE for this frame), then it will complete transmission of the current buffer and then update the status of the current (first) TDTE with the BUFF and UFLO bits being set. This will cause the transmitter to be disabled (CSR0, TXON=0). The PCnet-32 controller will have to be re-initialized to restore the transmit function. The situation that matches this description implies that the system has not been able to stay ahead of the PCnet-32 controller in the transmit descriptor ring and therefore, the condition is treated as a fatal error. (To avoid this situation, the system should always set the transmit chain descriptor own bits in reverse order.) If the PCnet-32 controller does own the second TDTE in a chain, it will gradually empty the contents of the first buffer (as the bytes are needed by the transmit opera-
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tion), perform a single-cycle DMA transfer to update the status of the first descriptor (reset the OWN bit in TMD1), and then it may perform one data DMA access on the second buffer in the chain before executing another look-ahead operation (i.e. a look-ahead to the third descriptor.) The PCnet-32 controller can queue up to two frames in the transmit FIFO. Call them frame "X" and frame "Y", where "Y" is after "X". Assume that frame "X" is currently being transmitted. Because the PCnet-32 controller can perform look-ahead data transfer past the ENP of frame "X", it is possible for the PCnet-32 controller to completely transfer the data from a buffer belonging to frame "Y" into the FIFO even though frame "X" has not yet been completely transmitted. At the end of this "Y" buffer data transfer, the PCnet-32 controller will write intermediate status (change the OWN bit to a zero) for the "Y" frame buffer, if frame "Y" uses data chaining. The last TDTE for the "X" frame (containing ENP) has not yet been written, since the "X" frame has not yet been completely transmitted. Note that the PCnet-32 controller has, in this instance, returned ownership of a TDTE to the host out of a "normal" sequence. For this reason, it becomes imperative that the host system should never read the Transmit DTE ownership bits out of order. There should be no problems for software which processes buffers in sequence, waiting for ownership before proceeding. If an error occurs in the transmission before all of the bytes of the current buffer have been transferred, then TMD2 and TMD1 of the current buffer will be written. In such a case, data transfers from the next buffer will not commence. Instead, following the TMD2/TMD1 update, the PCnet-32 controller will go to the next transmit frame, if any, skipping over the rest of the frame which experienced an error, including chained buffers. This is done by returning to the polling microcode where PCnet-32 controller will immediately access the next descriptor and find the condition OWN=1 and STP=0 as described earlier. As described for that case, the PCnet-32 controller will reset the own bit for this descriptor and continue in like manner until a descriptor with OWN=0 (no more transmit frames in the ring) or OWN=1 and STP=1 (the first buffer of a new frame) is reached. At the end of any transmit operation, whether successful or with errors, immediately following the completion of the descriptor updates, the PCnet-32 controller will al ways perform another poll operation. As described earlier, this poll operation will begin with a check of the current RDTE, unless the PCnet-32 controller already owns that descriptor. Then the PCnet-32 controller will proceed to polling the next TDTE. If the transmit descriptor OWN bit has a zero value, then the PCnet-32 controller will resume poll
time count incrementing. If the transmit descriptor OWN bit has a value of ONE, then the PCnet-32 controller will begin filling the FIFO with transmit data and initiate a transmission. This end-of-operation poll coupled with the TDTE look-ahead operation allows the PCnet-32 controller to avoid inserting poll time counts between successive transmit frames. Whenever the PCnet-32 controller completes a transmit frame (either with or without error) and writes the status information to the current descriptor, then the TINT bit of CSR0 is set to indicate the completion of a transmission. This causes an interrupt signal if the IENA bit of CSR0 has been set and the TINTM bit of CSR3 is reset. Receive Descriptor Table Entry (RDTE) If the PCnet-32 controller does not own both the current and the next Receive Descriptor Table Entry then the PCnet-32 controller will continue to poll according to the polling sequence described above. If the receive descriptor ring length is 1, then there is no next descriptor to be polled. If a poll operation has revealed that the current and the next RDTE belong to the PCnet-32 controller then additional poll accesses are not necessary. Future poll operations will not include RDTE accesses as long as the PCnet-32 controller retains ownership of the current and the next RDTE. When receive activity is present on the channel, the PCnet-32 controller waits for the complete address of the message to arrive. It then decides whether to accept or reject the frame based on all active addressing schemes. If the frame is accepted the PCnet-32 controller checks the current receive buffer status register CRST (CSR41) to determine the ownership of the current buffer. If ownership is lacking, then the PCnet-32 controller will immediately perform a (last ditch) poll of the current RDTE. If ownership is still denied, then the PCnet-32 controller has no buffer in which to store the incoming message. The MISS bit will be set in CSR0 and an interrupt will be generated if INEA=1 (CSR0) and MISSM=0 (CSR3). Another poll of the current RDTE will not occur until the frame has finished. If the PCnet-32 controller sees that the last poll (either a normal poll, or the last-ditch effort described in the above paragraph) of the current RDTE shows valid ownership, then it proceeds to a poll of the next RDTE. Following this poll, and regardless of the outcome of this poll, transfers of receive data from the FIFO may begin. Regardless of ownership of the second receive descriptor, the PCnet-32 controller will continue to perform receive data DMA transfers to the first buffer, using burst-cycle DMA transfers. If the frame length
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exceeds the length of the first buffer, and the PCnet-32 controller does not own the second buffer, ownership of the current descriptor will be passed back to the system by writing a zero to the OWN bit of RMD1 and status will be written indicating buffer (BUFF=1) and possibly overflow (OFLO=1) errors. If the frame length exceeds the length of the first (current) buffer, and the PCnet-32 controller does own the second (next) buffer, ownership will be passed back to the system by writing a zero to the OWN bit of RMD1 when the first buffer is full. Receive data transfers to the second buffer may occur before the PCnet-32 controller proceeds to look ahead to the ownership of the third buffer. Such action will depend upon the state of the FIFO when the status has been updated on the first descriptor. In any case, look-ahead will be performed to the third buffer and the information gathered will be stored in the chip, regardless of the state of the ownership bit. As in the transmit flow, lookahead operations are performed only once. This activity continues until the PCnet-32 controller recognizes the completion of the frame (the last byte of this receive message has been removed from the FIFO). The PCnet-32 controller will subsequently update the current RDTE status with the end of frame (ENP) indication set, write the message byte count (MCNT) of the complete frame into RMD2 and overwrite the "current" entries in the CSRs with the "next" entries.
-- Error detection (physical medium transmission errors) s Media access management. -- Medium allocation (collision avoidance) -- Contention resolution (collision handling) Transmit and Receive Message Data Encapsulation The MAC engine provides minimum frame size enforcement for transmit and receive frames. When APAD_XMT = 1 (CSR4[11]), transmit messages will be padded with sufficient bytes (containing 00h) to ensure that the receiving station will observe an information field (destination address, source address, length/type, data and FCS) of 64 bytes. When ASTRP_RCV = 1 (CSR4[10]), the receiver will automatically strip pad bytes from the received message by observing the value in the length field, and stripping excess bytes if this value is below the minimum data size (46 bytes). Both features can be independently overridden to allow illegally short (less than 64 bytes of frame data) messages to be transmitted and/or received. Use of this feature decreases bus usage because the pad bytes are not transferred into or out of host memory. Framing (Frame Boundary Delimitation, Frame Synchronization) The MAC engine will autonomously handle the construction of the transmit frame. Once the Transmit FIFO has been filled to the predetermined threshold (set by XMTSP in CSR80), and providing access to the channel is currently permitted, the MAC engine will commence the 7-byte preamble sequence (10101010b, where first bit transmitted is a 1). The MAC engine will subsequently append the Start Frame Delimiter (SFD) byte (10101011b) followed by the serialized data from the Transmit FIFO. Once the data has been completed, the MAC engine will append the FCS (most significant bit first) which was computed on the message (destination address, source address, length field, data field, and pad (if applicable)). Note that the user is responsible for the correct ordering and content in each of the fields in the frame, including the destination address, source address, length/type and frame data. The receive section of the MAC engine will detect an incoming preamble sequence and lock to the encoded clock. The internal MENDEC will decode the serial bit stream and present this to the MAC engine. The MAC will discard the first 8-bits of information before searching for the SFD sequence. Once the SFD is detected, all subsequent bits are treated as part of the frame. The MAC engine will inspect the length field to ensure minimum frame size, strip unnecessary pad characters (if enabled), and pass the remaining bytes through the Receive FIFO to the host. If pad stripping is performed, the MAC engine will also strip the received FCS bytes,
Media Access Control
The Media Access Control engine incorporates the essential protocol requirements for operation of a compliant Ethernet/802.3 node, and provides the interface between the FIFO subsystem and the Manchester Encoder/ Decoder (MENDEC). The MAC engine is fully compliant to Section 4 of ISO/ IEC 8802-3 (ANSI/IEEE Standard 1990 Second edition) and ANSI/IEEE 802.3 (1985). The MAC engine provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. These include the ability to disable retries after a collision, dynamic FCS generation on a frame-by-frame basis, and automatic pad field insertion and deletion to enforce minimum frame size attributes and reduces bus bandwidth use. The two primary attributes of the MAC engine are: s Transmit and receive message data encapsulation. -- Framing (frame boundary delimitation, frame synchronization) -- Addressing (source and destination address handling)
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although the normal FCS computation and checking will occur. Note that apart from pad stripping, the frame will be passed unmodified to the host. If the length field has a value of 46 or greater, the MAC engine will not attempt to validate the length against the number of bytes contained in the message. If the frame terminates or suffers a collision before 64 bytes of information (after SFD) have been received, the MAC engine will automatically delete the frame from the Receive FIFO, without host intervention. Addressing (Source and Destination Address Handling) The first 6 bytes of information after SFD will be interpreted as the destination address field. The MAC engine provides facilities for physical, logical (multicast) and broadcast address reception. In addition, multiple physical addresses can be constructed (perfect address filtering) using external logic in conjunction with the EADI interface. Error Detection (Physical Medium Transmission Errors) The MAC engine provides several facilities which report and recover from errors on the medium. In addition, the network is protected from gross errors due to inability of the host to keep pace with the MAC engine activity. On completion of transmission, the following transmit status is available in the appropriate TMD and CSR areas: s The number of transmission retry attempts (ONE, MORE or RTRY). s Whether the MAC engine had to Defer (DEF) due to channel activity. s Excessive deferral (EXDEF), indicating that the transmitter has experienced Excessive Deferral on this transmit frame, where Excessive Deferral is defined in ISO 8802-3 (IEEE/ANSI 802.3). s Loss of Carrier (LCAR) indicates that there was an interruption in the ability of the MAC engine to monitor its own transmission. Repeated LCAR errors indicate a potentially faulty transceiver or network connection. s Late Collision (LCOL) indicates that the transmission suffered a collision after the slot time. This is indicative of a badly configured network. Late collisions should not occur in a normal operating network. s Collision Error (CER) indicates that the transceiver did not respond with an SQE Test message within the predetermined time after a transmission completed. This may be due to a failed transceiver, disconnected or faulty transceiver drop cable, or the
fact the transceiver does not support this feature (or it is disabled). In addition to the reporting of network errors, the MAC engine will also attempt to prevent the creation of any network error due to the inability of the host to service the MAC engine. During transmission, if the host fails to keep the Transmit FIFO filled sufficiently, causing an underflow, the MAC engine will guarantee the message is either sent as a runt packet (which will be deleted by the receiving station) or has an invalid FCS (which will also cause the receiver to reject the message). The status of each receive message is available in the appropriate RMD and CSR areas. FCS and Framing errors (FRAM) are reported, although the received frame is still passed to the host. The error will only be reported if an FCS error is detected and there are a non integral number of bytes in the message. The MAC engine will ignore up to 7 additional bits at the end of a message (dribbling bits), which can occur under normal network operating conditions. The reception of 8 additional bits will cause the MAC engine to deserialize the entire byte, and will result in the received message and FCS being modified. The PCnet-32 controller can handle up to 7 dribbling bits when a received frame terminates. During the reception, the FCS is generated on every serial bit (including the dribbling bits) coming from the cable, although the internally saved FCS value is only updated on the eighth bit (on each byte boundary). The framing error is reported to the user as follows: s If the number of dribbling bits are 1 to 7 and there is no CRC (FCS) error, then there is no Framing error (FRAM = 0). s If the number of dribbling bits are 1 to 7 and there is a CRC (FCS) error, then there is also a Framing error (FRAM = 1). s If the number of dribbling bits = 0, then there is no Framing error. There may or may not be a CRC (FCS) error. Counters are provided to report the Receive Collision Count and Runt Packet Count for network statistics and utilization calculations. Note that if the MAC engine detects a received frame which has a 00b pattern in the preamble (after the first 8-bits which are ignored), the entire frame will be ignored. The MAC engine will wait for the network to go inactive before attempting to receive additional frames. Media Access Management The basic requirement for all stations on the network is to provide fairness of channel allocation. The 802.3/ Ethernet protocols define a media access mechanism which permits all stations to access the channel with equality. Any node can attempt to contend for the channel by waiting for a predetermined time (Inter
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Packet Gap internal) after the last activity, before transmitting on the media. The channel is a multidrop communications media (with various topological configurations permitted) which allows a single station to transmit and all other stations to receive. If two nodes simultaneously contend for the channel, their signals will interact causing loss of data, defined as a collision. It is the responsibility of the MAC to attempt to avoid and recover from a collision, to guarantee data integrity for the end-to-end transmission to the receiving station. Medium Allocation The IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990) requires that the CSMA/CD MAC monitor the medium for traffic by watching for carrier activity. When carrier is detected, the media is considered busy, and the MAC should defer to the existing message. The ISO 8802-3 (IEEE/ANSI 802.3) Standard also allows optional two-par t deferral after a receive message. See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1: "Note: It is possible for the PLS carrier sense indication to fail to be asserted during a collision on the media. If the deference process simply times the inter packet gap based on this indication it is possible for a short inter packet gap to be generated, leading to a potential reception failure of a subsequent frame. To enhance system robustness the following optional measures, as specified in 4.2.8, are recommended when Inter Frame Spacing Part 1 is other than zero: 1. Upon completing a transmission, start timing the interpacket gap, as soon as transmitting and carrier sense are both false. 2. When timing an inter packet gap following reception, reset the inter packet gap timing if carrier sense becomes true during the first 2/3 of the inter-packet gap timing interval. During the final 1/ 3 of the interval the timer shall not be reset to en sure fair access to the medium. An initial period shorter than 2/3 of the interval is permissible in cluding zero. The MAC engine implements the optional receive two part deferral algorithm, with a first part inter-framespacing time of 6.0 s. The second part of the interframe-spacing interval is therefore 3.6 s. The PCnet-32 controller will perform the two part deferral algorithm as specified in Section 4.2.8 (Process Deference). The Inter Packet Gap (IPG) timer will start timing the 9.6 s Inter Frame Spacing after the receive carrier is de-asserted. During the first part deferral (Inter Frame Spacing Par t1 - IFS1) the PCnet-32 controller will defer any pending transmit frame and respond to the receive message. The IPG counter will be reset to zero continuously until the carrier de-
asserts, at which point the IPG counter will resume the 9.6 s count once again. Once the IFS1 period of 6.0 s has elapsed, the PCnet-32 controller will begin timing the second part deferral (Inter Frame Spacing Part 2 - IFS2) of 3.6 s. Once IFS1 has completed, and IFS2 has commenced, the PCnet-32 controller will not defer to a receive frame if a transmit frame is pending. This means that the PCnet-32 controller will not attempt to receive the receive frame, since it will start to transmit, and generate a collision at 9.6 s. The PCnet-32 controller will guarantee to complete the preamble (64-bit) and jam (32-bit) sequence before ceasing transmission and invoking the random back-off algorithm. T h i s t r a n s m i t t w o p a r t d e fe r r a l a l g o r i t h m i s implemented as an option which can be disabled using the DXMT2PD bit in CSR3. Two part deferral after transmission is useful for ensuring that severe IPG shrinkage cannot occur in specific circumstances, causing a transmit message to follow a receive message so closely as to make them indistinguishable. During the time period immediately after a transmission has been completed, the external transceiver (in the case of a standard AUI connected device), should generate the SQE Test message (a nominal 10 MHz burst of 5-15 Bit Times duration) on the CI pair (within 0.6 1.6 s after the transmission ceases). During the time period in which the SQE Test message is expected the PCnet-32 controller will not respond to receive carrier sense. See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1)): "At the conclusion of the output function, the DTE opens a time window during which it expects to see the signal_quality_error signal asserted on the Control In circuit. The time window begins when the CARRIER_ STATUS becomes CARRIER_OFF. If execution of the output function does not cause CARRIER_ON to occur, no SQE test occurs in the DTE. The duration of the window shall be at least 4.0 s but no more than 8.0 s. During the time window, the Carrier Sense Function is inhibited." The PCnet-32 controller implements a carrier sense "blinding" period within 0 s-4.0 s from de-assertion of carrier sense after transmission. This effectively means that when transmit two part deferral is enabled (DXMT2PD is cleared) the IFS1 time is from 4 s to 6 s after a transmission. However, since IPG shrinkage below 4 s will rarely be encountered on a correctly configured networks, and since the fragment size will be larger than the 4 s blinding window, then the IPG counter will be reset by a worst case IPG shrinkage/ fragment scenario and the PCnet-32 controller will defer its transmission. In addition, the PCnet-32 controller will not restart the "blinding" period if carrier
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is detected within the 4.0 s - 6.0 s IFS1 period, but will commence timing of the entire IFS1 period. Contention Resolution (Collision Handling) Collision detection is performed and reported to the MAC engine by the integrated Manchester Encoder/ Decoder (MENDEC). If a collision is detected before the complete preamble/ SFD sequence has been transmitted, the MAC Engine will complete the preamble/SFD before appending the jam sequence. If a collision is detected after the preamble/SFD has been completed, but prior to 512 bits being transmitted, the MAC Engine will abort the tr an s m i s s i on , a nd a p p en d t he j a m s e qu e nc e immediately. The jam sequence is a 32-bit all zeroes pattern. The MAC Engine will attempt to transmit a frame a total of 16 times (initial attempt plus 15 retries) due to normal collisions (those within the slot time). Detection of c ollis ion will caus e the tra nsmis sion to be rescheduled, dependent on the back-off time that the MAC Engine computes. If a single retry was required, the ONE bit will be set in the Transmit Frame Status. If more than one retry was required, the MORE bit will be set. If all 16 attempts experienced collisions, the RTRY bit will be set (ONE and MORE will be clear), and the transmit message will be flushed from the FIFO. If retries have been disabled by setting the DRTY bit in CSR15, the MAC Engine will abandon transmission of the frame on detection of the first collision. In this case, only the RTRY bit will be set and the transmit message will be flushed from the FIFO. If a collision is detected after 512 bit times have been transmitted, the collision is termed a late collision. The MAC Engine will abort the transmission, append the jam sequence and set the LCOL bit. No retry attempt will be scheduled on detection of a late collision, and the transmit message will be flushed from the FIFO. The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires use of a "truncated binary exponential back-off" algorithm which provides a controlled pseudo random mechanism to enforce the collision back-off interval, be-fore retransmission is attempted. See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5: "At the end of enforcing a collision (jamming), the CSMA/CD sublayer delays before attempting to retransmit the frame. The delay is an integer multiple of slotTime. The number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer r in the range: 0 r < 2k -1 where k = min (n,10)."
The PCnet-32 controller provides an alternative algorithm, which suspends the counting of the slot time/IPG during the time that receive carrier sense is detected. This aids in networks where large numbers of nodes are present, and numerous nodes can be in collision. It effectively accelerates the increase in the back-off time in busy networks, and allows nodes not involved in the collision to access the channel whilst the colliding nodes await a reduction in channel activity. Once channel activity is reduced, the nodes resolving the collision time out their slot time counters as normal.
Manchester Encoder/Decoder (MENDEC)
The integrated Manchester Encoder/Decoder provides the PLS (Physical Layer Signaling) functions required for a fully compliant ISO 8802-3 (IEEE/ANSI 802.3) station. The MENDEC provides the encoding function for data to be transmitted on the network using the high accuracy on-board oscillator, driven by either the crystal oscillator or an external CMOS level compatible clock. The MENDEC also provides the decoding function from data received from the network. The MENDEC contains a Power On Reset (POR) circuit, which ensures that all analog portions of the PCnet-32 controller are forced into their correct state during power up, and prevents erroneous data transmission and/or reception during this time. External Crystal Characteristics When using a crystal to drive the oscillator, the crystal specification shown in Table 26 may be used to ensure less than 0.5 ns jitter at the transmit outputs.
Table 26. External Crystal Specification
Parameter Min Nom Max Unit
1.Parallel Resonant Frequency 2.Resonant Frequency Error -50
20 +50 +40 50
MHz PPM PPM pF
3.Change in Resonant Frequency -40 With Respect To Temperature 20 (0xC-70xC)* 4.Crystal Load Capacitance 5.Motional Crystal Capacitance (C1) 6.Series Resistance 7.Shunt Capacitance 8.Drive Level 0.022
pF 25 7 TBD ohm pF mW
*Requires trimming spec,: no trim is 50 ppm total. External Clock Drive Characteristics When driving the oscillator from an external clock source, XTAL2 must be left floating (unconnected). An external clock having the following characteristics must be used to ensure less than 0.5 ns jitter at the transmit outputs. See Table 27.
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Table 27. External Clock Drive Characteristics
Clock Frequency: Rise/Fall Time (tR/tF): XTAL1 HIGH/LOW Time
(tHIGH/tLOW):
Receiver Path The principal functions of the Receiver are to signal the PCnet-32 controller that there is information on the receive pair, and separate the incoming Manchester encoded data stream into clock and NRZ data. The Receiver section (see Figure 30) consists of two parallel paths. The receive data path is a zero threshold, wide bandwidth line receiver. The carrier path is an offset threshold bandpass detecting line receiver. Both receivers share common bias networks to allow operation over a wide input common mode range. Input Signal Conditioning Transient noise pulses at the input data stream are rejected by the Noise Rejection Filter. Pulse width rejection is proportional to transmit data rate. The Carrier Detection circuitry detects the presence of an incoming data frame by discerning and rejecting noise from expected Manchester data, and controls the stop and start of the phase-lock loop during clock acqui siti on.Clock acqui sitio n r equir es a vali d Manchester bit pattern of 1010b to lock onto the incoming message. When input amplitude and pulse width conditions are met at DI/RXD, the internal enable signal from the MENDEC to controller (IRXCRS) is asserted and clock acquisition cycle is initiated. Clock Acquisition When there is no activity at DI (receiver is idle), the receive oscillator is phase locked to the internal transmit clock. The first negative clock transition (bit cell center of first valid Manchester "0") after IRXCRS is asser ted interrupts the receive oscillator. The oscillator is then restarted at the second Manchester "0" (bit time 4) and phase locked to it. As a result, the MENDEC acquires the clock from the incoming Manchester bit pattern in bit times with a "1010" Manchester bit pattern. ISRDCLK and IRXDAT are enabled 1/4 bit time after clock acquisition in bit cell 5. IRXDAT is at a HIGH state when the receiver is idle (no ISRDCLK). IRXDAT however, is undefined when clock is acquired and may remain HIGH or change to LOW state whenever ISRDCLK is enabled. At 1/4 bit time through bit cell 5,the controller portion of the PCnet-32 controller sees the first ISRDCLK transition. This also strobes in the incoming fifth bit to the MENDEC as Manchester "1". IRXDAT may make a transition after the ISRDCLK rising edge bit cell 5, but its state is still undefined. The Manchester"1" at bit 5 is clocked to IRXDAT output at 1/ 4 bit time bit cell 6.
20 MHz 0.01% < 6 ns from 0.5 V to VDD-0.5 20 ns min
XTAL1 Falling Edge to Falling Edge Jitter:
< 0.2 ns at 2.5 V input (VDD/2)
MENDEC Transmit Path The transmit section encodes separate clock and NRZ data input signals into a standard Manchester encoded serial bit stream. The transmit outputs (DO/TXD) are designed to operate into terminated transmission lines. When operating into a 78 W terminated transmission line, the transmit signaling meets the required output levels and skew for Cheaper net, Ether net and IEEE-802.3. Transmitter Timing and Operation A 20 MHz fundamental mode crystal oscillator provides the basic timing reference for the MENDEC portion of the PCnet-32 controller. The crystal is divided by two, to create the internal transmit clock reference. Both clocks are fed into the MENDEC's Manchester Encoder to generate the transitions in the encoded data stream. The internal transmit clock is used by the MENDEC to internally synchronize the Internal Transmit Data (ITXDAT) from the controller and Internal Transmit Enable (ITXEN). The internal transmit clock is also used as a stable bit rate clock by the receive section of the MENDEC and controller. The oscillator requires an external 0.01% timing reference. The accuracy requirements, if an external crystal is used are tighter because allowance for the on-board parasitics must be made to deliver a final accuracy of 0.01%. Transmission is enabled by the controller. As long as the ITXEN request remains active, the serial output of the controller will be Manchester encoded and appear at DO/TXD. When the internal request is dropped by the controller, the differential transmit outputs go to one of two idle states, dependent on TSEL in the Mode Register (CSR15, bit 9):
TSEL LOW:
The idle state of DO/TXD yields "zero" differential to operate transformer-coupled loads. In this idle state, DO+/TXD+ is positive with respect to DO-/TXD- (logical HIGH).
TSEL HIGH:
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DI/RXD
Data Receiver
Manchester Decoder
IRXDAT*
ISRDCLK*
Noise Reject Filter
Carrier Detect Circuit
IRXCRS*
*Internal signal
18219-37
Figure 30. Receive Block Diagram
PLL Tracking After clock acquisition, the phase-locked clock is compared to the incoming transition at the bit cell center (BCC) and the resulting phase error is applied to a correction circuit. This circuit ensures that the phaselocked clock remains locked on the received signal. Individual bit cell phase corrections of the Voltage Controlled Oscillator (VCO) are limited to 10% of the phase difference between BCC and phase-locked clock. Hence, input data jitter is reduced in ISRDCLK by 10 to 1. Carrier Tracking and End of Message The carrier detection circuit monitors the DI inputs after IRXCRS is asserted for an end of message. IRXCRS de-asserts 1 to 2 bit times after the last positive transition on the incoming message. This initiates the end of reception cycle. The time delay from the last rising edge of the message to IRXCRS deassert allows the last bit to be strobed by ISRDCLK and transferred to the controller section, but prevents any extra bit(s) at the end of message. Data Decoding The data receiver is a comparator with clocked output to minimize noise sensitivity to the DI/RXD inputs. Input error is less than 35 mV to minimize sensitivity to input rise and fall time. ISRDCLK strobes the data receiver output at 1/4 bit time to determine the value of the Manchester bit, and clocks the data out on IRXDAT on the following ISRDCLK. The data receiver also generates the signal used for phase detector comparison to the internal MENDEC voltage controlled oscillator (VCO).
Jitter Tolerance Definition The MENDEC utilizes a clock capture circuit to align its internal data strobe with an incoming bit stream. The clock acquisition circuitry requires four valid bits with the values 1010b. Clock is phase-locked to the negative transition at the bit cell center of the second "0" in the pattern. Since data is strobed at 1/4 bit time, Manchester transitions which shift from their nominal placement through 1/4 bit time will result in improperly decoded data. With this as the criteria for an error, a definition of "Jitter Handling" is: The peak deviation approaching or crossing 1/4 bit cell position from nominal input transition, for which the MENDEC section will properly decode data.
Attachment Unit Interface(AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA (Physical Medium Attachment) interface which effectively connects the DTE to a MAU. The differential interface provided by the PCnet-32 controller is fully compliant to Section 7 of ISO 8802-3 (ANSI/IEEE 802.3). After the PCnet-32 controller initiates a transmission it will expect to see data "looped-back" on the DI pair (when the AUI port is selected). This will internally generate a "carrier sense", indicating that the integrity of the data path to and from the MAU is intact, and that the MAU is operating correctly. This "carrier sense" signal must be asserted within TBD bit times after the first transmitted bit on DO (when using the AUI port). If "carrier sense" does not become active in response to the data transmission, or becomes inactive before the end of transmission, the loss of carrier (LCAR) error bit
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will be set in the Transmit Descriptor Ring (TMD2, bit27) after the frame has been transmitted. Differential Input Terminations The differential input for the Manchester data (DI) is externally terminated by two 40.2 W 1% resistors and one optional common-mode bypass capacitor, as shown in the Differential Input Termination diagram below. The differential input impedance, ZIDF, and the common-mode input impedance, ZICM, are specified so that the Ethernet specification for cable termination impedance is met using standard 1% resistor terminators. If SIP devices are used, 39 W is also a suitable value. The CI differential inputs are terminated in exactly the same way as the DI pair.
T-MAU gets reset during power-up by H_RESET, by S_RESET when reset port is read, or by asserting the RESET pin. T-MAU is not reset by STOP. Twisted Pair Transmit Function The differential driver circuitry in the TXD and TXP pins provides the necessary electrical driving capability and the pre-distortion control for transmitting signals over maximum length Twisted Pair cable, as specified by the 10BASE-T supplement to the ISO 8802-3 (IEEE/ ANSI 802.3) Standard. The transmit function for data output meets the propagation delays and jitter specified by the standard. Twisted Pair Receive Function The receiver complies with the receiver specifications of the ISO 8802-3 (IEEE/ANSI 802.3) 10BASE-T Standard, including noise immunity and received signal rejection criteria (`Smart Squelch'). Signals meeting this criteria appearing at the RXD differential input pair are routed to the MENDEC. The receiver function meets the propagation delays and jitter requirements specified by the standard. The receiver squelch level drops to half its threshold value after unsquelch to allow reception of minimum amplitude signals and to offset carr ier fade in the event of worst case signal attenuation and crosstalk noise conditions. Note that the 10BASE-T Standard defines the receive input amplitude at the external Media Dependent Interface (MDI). Filter and transfor mer loss are not specified. The T-MAU receiver squelch levels are defined to account for a 1 dB insertion loss at 10 MHz, which is typical for the type of receive filters/ transformers employed. Normal 10BASE-T compatible receive thresholds are employed when the LRT (CSR15[9]) bit is LOW. When the LRT bit is set (HIGH), the Low Receive Threshold option is invoked, and the sensitivity of the T-MAU receiver is increased. This allows longer line lengths to be employed, exceeding the 100 m target distance of normal 10BASE-T (assuming typical 24 AWG cable). The increased receiver sensitivity compensates for the increased signal attenuation caused by the additional cable distance. However, making the receiver more sensitive means that it is also more susceptible to extraneous noise, primarily caused by coupling from co-resident services (crosstalk). For this reason, it is recommended that when using the Low Receive Threshold option that the service should be installed on 4-pair cable only. Multipair cables within the same outer sheath have lower crosstalk attenuation, and may allow noise emitted from adjacent pairs to couple into the receive pair, and be of sufficient amplitude to falsely unsquelch the T-MAU.
AUI Isolation Transformer DI+
PCnet 32
DI-
40.2
40.2
0.01 F to 0.1 F
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Figure 31. AUI Differential Input Termination
Collision Detection A MAU detects the collision condition on the network and generates a differential signal at the CI inputs. This collision signal passes through an input stage which detects signal levels and pulse duration. When the signal is detected by the MENDEC it sets the ICLSN line HIGH. The condition continues for approximately 1.5 bit times after the last LOW-to-HIGH transition on CI.
Twisted-Pair Transceiver (T-MAU)
The T-MAU implements the Medium Attachment Unit (MAU) functions for the Twisted Pair Medium, as specified by the supplement to ISO 8802-3 (IEEE/ANSI 802.3) standard (Type 10BASE-T). The T-MAU provides twisted pair driver and receiver circuits, including on-board transmit digital predistortion and receiver squelch and a number of additional features including Link Status indication, Automatic Twisted Pair Receive Polarity Detection/Correction and Indication, Receive Carrier Sense, Transmit Active and Collision Present indication.
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Link Test Function The link test function is implemented as specified by 10BASE-T standard. During periods of transmit pair inactivity, 'Link beat pulses' will be periodically sent over the twisted pair medium to constantly monitor medium integrity. When the link test function is enabled (DLNKTST bit in CSR15 is cleared), the absence of link beat pulses and receive data on the RXD pair will cause the T-MAU to go into a link fail state. In the link fail state, data transmission, data reception, data loopback and the collision detection functions are disabled, and remain disabled until valid data or >5 consecutive link pulses appear on the RXD pair. During link fail, the Link Status signal is inactive. When the link is identified as functional, the Link Status signal is asserted. The LNKST pin displays the Link Status signal by default. Transmission attempts during Link Fail state will produce no network activity and will produce LCAR and CERR error indications. In order to inter-operate with systems which do not implement Link Test, this function can be disabled by setting the DLNKTST bit in CSR15. With link test disabled, the data driver, receiver and loopback functions as well as collision detection remain enabled regardless of the presence or absence of data or link pulses on the RXD pair. Link Test pulses continue to be sent regardless of the state of the DLNKTST bit. Polarity Detection and Reversal The T-MAU receive function includes the ability to invert the polarity of the signals appearing at the RXD pair if the polarity of the received signal is reversed (such as in the case of a wiring error). This feature allows data frames received from a reverse wired RXD input pair to be corrected in the T-MAU prior to transfer to the MENDEC. The polarity detection function is activated following H_RESET or Link Fail, and will reverse the receive polarity based on both the polarity of any pr ev i ou s l in k be at p ul s es a nd th e po la r i ty o f subsequent frames with a valid End Transmit Delimiter (ETD). When in the Link Fail state, the T-MAU will recognize link beat pulses of either positive or negative polarity. Exit from the Link Fail state is made due to the reception of 5-6 consecutive link beat pulses of identical polarity. On entry to the Link Pass state, the polarity of the last 5 link beat pulses is used to determine the initial receive polarity configuration and the receiver is reconfigured to subsequently recognize only link beat pulses of the previously recognized polarity. Positive link beat pulses are defined as received signal with a positive amplitude greater than 585 mV (LRT = HIGH) with a pulse width of 60 ns-200 ns. This positive
excursion may be followed by a negative excursion. This definition is consistent with the expected received signal at a correctly wired receiver, when a link beat pulse which fits the template of Figure 14-12 of the 10BASE-T Standard is generated at a transmitter and passed through 100 m of twisted pair cable. Negative link beat pulses are defined as received signals with a negative amplitude greater than 585 mV with a pulse width of 60 ns-200 ns. This negative excursion may be followed by a positive excursion. This definition is consistent with the expected received signal at a reverse wired receiver, when a link beat pulse which fits the template of Figure 14-12 in the 10BASE-T Standard is generated at a transmitter and passed through 100 m of twisted pair cable. The polarity detection/correction algorithm will remain "armed" until two consecutive frames with valid ETD of identical polarity are detected. When "armed", the receiver is capable of changing the initial or previous polarity configuration based on the ETD polarity. On receipt of the first frame with valid ETD following H_RESET or link fail, the T-MAU will utilize the inferred polarity information to configure its RXD input, regardless of its previous state. On receipt of a second frame with a valid ETD with correct polarity, the detection/correction algorithm will "lock-in" the received polarity. If the second (or subsequent) frame is not detected as confirming the previous polarity decision, the most recently detected ETD polarity will be used as the default. Note that frames with invalid ETD have no effect on updating the previous polarity decision. Once two consecutive frames with valid ETD have been received, the T-MAU will disable the detection/ correction algorithm until either a Link Fail condition occurs or H_RESET is activated. During polarity reversal, an internal POL signal will be active. During normal polarity conditions, this internal POL signal is inactive. The state of this signal can be read by software and/or displayed by LED when enabled by the LED control bits in the Bus Configuration Registers (BCR4-BCR7). Twisted Pair Interface Status Three signals (XMT, RCV and COL) indicate whether the T-MAU is transmitting, receiving, or in a collision state with both functions active simultaneously. These signals are internal signals and the behavior of the LED outputs depends on how the LED Output circuiting is programmed. The T-MAU will power up in the Link Fail state and the normal algorithm will apply to allow it to enter the Link Pass state. In the Link Pass state, transmit or receive activity will be indicated by assertion of RCV signal going active. If T-MAU is selected using the PORTSEL bits in CSR15, then when moving from AUI to T-MAU
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selection the T-MAU will be forced into the Link Fail state. In the Link Fail state, XMT, RCV and COL are inactive. Collision Detect Function Activity on both twisted pair signals RXD and TXD constitutes a collision, thereby causing the COL signal to be activated. (COL is used by the LED control circuits) COL will remain active until one of the two colliding signals changes from active to idle. However, transmission attempt in Link Fail state results in LCAR and CERR indication. COL stays active for 2-bit times at the end of a collision. Signal Quality Error (SQE) Test (Heartbeat) Function The SQE function is disabled when the 10BASE-T port is selected. Jabber Function The Jabber function inhibits the twisted pair transmit function of the T-MAU if the TXD circuit is active for an excessive period (20 ms-150 ms). This prevents any one node from disrupting the network due to a 'stuckon' or faulty transmitter. If this maximum transmit time is exceeded, the T-MAU transmitter circuitr y is disabled, the JAB bit is set (CSR4, bit1), the COL signal is asserted. Once the transmit data stream to the T-MAU is removed, an "unjab" time of 250 ms-750 ms will elapse before the T-MAU COL and re-enables the transmit circuitry. Power Down The T-MAU circuitry can be made to go into power savings mode. This feature is useful in battery powered or low duty cycle systems. The T-MAU will go into power
down mode when H_RESET is active, coma mode is active, or the T-MAU is not selected. Refer to the Power Savings Modes section for descriptions of the various power down modes. Any of the three conditions listed above resets the internal logic of the T-MAU and places the device into power down mode. In this mode, the Twisted Pair driver pins (TXD,TXP) are driven LOW, and the internal TMAU status signals (LNKST, RCVPOL, XMT, RCV and COL) signals are inactive. Once H_RESET ends, coma mode is disabled, and the T-MAU is selected. The T-MAU will remain in the reset state for up to 10 s. Immediately after the reset condition is removed, the T-MAU will be forced into the Link Fail state. The T-MAU will move to the Link Pass state only after 5 - 6 link beat pulses and/or a single received message is detected on the RD pair. In snooze mode, the T-MAU receive circuitry will remain enabled even while the SLEEP pin is driven LOW. The T-MAU circuitry will always go into power down mode if H_RESET is asserted, coma mode is enabled, or the T-MAU is not selected. 10BASE-T Interface Connection Figure 32 shows the proper 10BASE-T network interface design. Refer to the PCnet Family Technical Manual (PID # 18216A) for more design details, and refer to Appendix A for a list of compatible 10BASE-T filter/ transformer modules. Note that the recommended resistor values and filter and transformer modules are the same as those used by the IMR (Am79C980) and the IMR+ (Am79C981).
TXD+ TXP+ TXD-
61.9 422 61.9 422 1.21 K
Filter & Transformer Module 1:1 XMT Filter 1:1 RCV Filter
RJ45 Connector
TD+ TD1 2
PCnet-32
TXPRXD+ RXD-
RD+ RD-
3 6
100
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Figure 32. 10BASE-T Interface Connection
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IEEE 1149.1 Test Access Port Interface
An IEEE 1149.1 compatible boundary scan Test Access Port is provided for board level continuity test and diagnostics. All digital input, output and input/ output pins are tested. Analog pins, including the AUI differential driver (DO) and receivers (DI, CI), and the crystal input (XTAL1/XTAL2) pins, are tested. The T-MAU drivers TXD, TXP and receiver RXD are also tested. The following is a brief summary of the IEEE 1149.1 compatible test functions implemented in the PCnet-32 controller. Boundary Scan Circuit The boundary scan test circuit requires four pins (TCK, TMS, TDI and TDO), defined as the Test Access Port (TAP). It includes a finite state machine (FSM), an instruction register, a data register array, and a power-on reset circuit. Internal pull-up resistors are provided for the TDI, TCK, and TMS pins. The TCK pin must not be left unconnected. The boundary scan circuit remains active during Sleep.
TAP FSM The TAP engine is a 16-state FSM, driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. This FSM is in its reset state at power-up or after H_RESET. An independent power-on reset circuit is provided to ensure the FSM is in the TEST_LOGIC_RESET state at power-up. Supported Instructions In addition to the minimum IEEE 1149.1 requirements (BYPASS, EXTEST, and SAMPLE instructions), three additional instr uctions (IDCODE, TRIBYP and SETBYP) are provided to further ease board-level testing. All unused instruction codes are reserved. See Table 28 for a summary of supported instructions. Instruction Register and Decoding Logic After H_RESET or S_RESET or STOP, the IDCODE instruction is always invoked. The decoding logic gives signals to control the data flow in the DATA registers according to the current instruction. Boundary Scan Register (BSR) Each BSR cell has two stages. A flip-flop and a latch are used for the SERIAL SHIFT STAGE and the PARALLEL OUTPUT STAGE, respectively.
Table 28. IEEE 1149.1 Supported Instruction Summary
Instruction Name EXTEST IDCODE SAMPLE TRIBYP SETBYP BYPASS External Test ID Code Inspection Sample Boundary Force Tristate Control Boundary To 1/0 Bypass Scan Description Selected Data Reg BSR ID REG BSR Bypass Bypass Bypass Mode Test Normal Normal Normal Test Normal Instruction Code 0000 0001 0010 0011 0100 1111
There are four possible operation modes in the BSR cell:
Bits 31-28: Bits 27-12: 1 2 3 4 Capture Bits 11-1: Shift Update System Function Bit 0: Manufacturer ID. The 11 bit manufacturer ID code for AMD is 00000000001 according to JEDEC Publication 106-A. Always a logic 1 Version Part number (0010 0100 0011 0000)
Other Data Register 1) BYPASS REG (1 Bit) 2) DEV ID REG (32 bits)
3) INSCAN0 This is an internal scan path for AMD internal testing use.
EADI (External Address Detection Interface)
This interface is provided to allow external address filtering. It is selected by setting the EADISEL bit in
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BCR2 to a ONE. This feature is typically utilized for terminal servers, bridges and/or router products. The EADI interface can be used in conjunction with external logic to capture the packet destination address from the serial bit stream as it arrives at the PCnet-32 controller, compare the captured address with a table of stored addresses or identifiers, and then determine whether or not the PCnet-32 controller should accept the packet. The EADI interface outputs are delivered directly from the NRZ decoded data and clock recovered by the Manchester decoder or input into the GPSI port. This allows the external address detection to be performed in p ara l le l wi th fr am e r e c ep ti o n a nd a dd r es s comparison in the MAC Station Address Detection (SAD) block of the PCnet-32 controller. SRDCLK is provided to allow clocking of the receive bit stream into the external address detection logic. SRDCLK runs only during frame reception activity. Once a received frame commences and data and clock are available from the decoder, the EADI logic will monitor the alternating ("1,0") preamble pattern until t h e t w o o n e s o f t h e S t a r t Fr a m e D e l i m i t e r ("1,0,1,0,1,0,1,1") are detected, at which point the SF/ BD output will be driven HIGH. The SF/BD signal will initially be LOW. The assertion of SF/BD is a signal to the external address detection logic that the SFD has been detected and that subsequent SRDCLK cycles will deliver packet data to the external logic. Therefore, when SF/BD is asserted, the external address matching logic should begin deserialization of the SRD data and send the resulting destination address to a content addressable memory (CAM) or other address detection device. In order to reduce the amount of logic external to the PCnet-32 controller for multiple address decoding systems, the SF/BD signal will toggle at each new byte boundary within the packet, subsequent to the SFD. This eliminates the need for externally supplying byte framing logic. The EAR pin should be driven LOW by the external address comparison logic to reject a frame. If an address match is detected by internal address comparison with either the Physical or Logical or broadcast Address contained within the PCnet-32 controller, then the frame will be accepted regardless of the condition of EAR. Internal address match is disabled when PROM (CSR15[15]) = 0, DRCVBC (CSR15[14]) = 1, DRCVPA (CSR15[13]) = 1 and Logical Address Filter (CSR8-CSR11) = 0.
When the EADISEL bit of BCR2 is set to a ONE and internal address match is disabled, then all incoming frames will be accepted by the PCnet-32 controller, unless the EAR pin becomes active during the first 64 bytes of the frame (excluding preamble and SFD). This allows external address lookup logic approximately 58 byte times after the last destination address bit is available to generate the EAR signal, assuming that the PCnet-32 controller is not configured to accept runt packets. EAR will be ignored after 64 byte times after the SFD. The frame will be accepted if EAR has not been asserted before this time. If Runt Packet Accept is enabled, then the EAR signal must be generated prior to the receive message completion, if packet rejection is to be guaranteed. Runt packet sizes could be as short as 12 byte times (assuming 6 bytes for source address, 2 bytes for length, no data, 4 bytes for FCS) after the last bit of the destination address is available. EAR must have a pulse width of at least 150 ns. When the EADISEL bit of BCR2 is set to a ONE and the PROM bit of the Mode Register is set to a ONE, then all incoming frames will be accepted by the PCnet-32 controller, regardless of any activity on the EAR pin. The EADI outputs continue to provide data throughout the reception of a packet. This allows the external logic to capture packet header information to determine protocol type, inter-networking information, and other useful data. The EADI interface will operate as long as the STRT bit in CSR0 is set, even if the receiver and/or transmitter are disabled by software (DTX and DRX bits in CSR15 are set). This configuration is useful as a semi-powerdown mode in that the PCnet-32 controller will not perform any power-consuming DMA operations. However, external circuitry can still respond to "control" frames on the network to facilitate remote node control. Table 29 summarizes the operation of the EADI interface.
Table 29. EADI Operations
PROM 1 0 0 EAR X 1 0 Required Timing No timing requirements No timing requirements Low for 150 ns within 512 bits after SFD Received Messages All Received Frames All Received Frames PCnet-32 Controller Internal Physical and Logical Address Matches
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General Purpose Serial Interface (GPSI)
The PCnet-32 controller is capable of providing a purely digital network interface in the form of the General Purpose Serial Interface. This interface matches the functionality provided by earlier AMD network controller products, such as the Am7990 LANCE, Am79C90 C-LANCE, Am79C900 ILACC c o n t r o l l e r, A m 7 9 C 9 4 0 M AC E c o n t r o l l e r, a n d Am79C960 PCnet-ISA controller. The GPSI interface is selected through the PORTSEL bits of the Mode register (CSR15) and enabled through the TSTSHDW bits of BCR18 (bits 3 and 4) or enabled through the GPSIEN bit in CSR124 (bit 4). The possible settings to invoke the GPSI mode are shown in Table 30.
Table 30. GPSI Mode Selection
TSTSHDW Value (BCR18 [4:3]) 00 PVALID (BCR19 [15]) 1 GPSIEN (CSR124[4]) 0 Operating Mode Normal Operating Mode GPSI Mode Reserved Reserved Normal Operating Mode GPSI Mode
mode is not active and therefore, the Software Relocatable Mode might assume that all 30 address bits are visible. But in a system that uses GPSI mode, the GPSI signals would likely all be hard-wired to the address pins, and, therefore, even though the device never made it into GPSI mode, it will still not be able to see the upper address bits. Therefore, it is always recommended that SRMA24 mode be invoked as described in the next paragraph: Software Relocatable Mode Address 24 mode is invoked by connecting the LED2/SRDCLK pin to a LOW level during H_RESET and during the execution of the Software Relocation operation. When the LED2/ SRDCLK pin is LOW during H_RESET and Software Relocatable Mode, then the device will be programmed to use 24 bits of addressing while snooping accesses on the bus during Software Relocatable Mode; In this case, the PCnet-32 controller will assume that bits A[31] through A[24] are matched at all times, regardless of the actual values on these pins. I/O Address Width 24 mode is invoked by writing a ONE to the IOAW24 bit of BCR21 (bit 8 of BCR21). This can be accomplished safely in either of two ways: 1. A Software Relocation operation can write a ONE to BCR21, bit 8. 2. A read of the EEPROM contents can write a ONE to BCR21, bit 8, if the EEPROM contents are correctly programmed. These two methods do NOT require a slave access to the PCnet-32 controller, and therefore may be performed in a system in which the GPSI signals are permanently connected to the A[31] through A[23] pins (assuming SRMA24 mode is invoked via the LED2/ SRDCLK pin to use method 1). The PCnet-32 controller upper address pins are reconfigured during GPSI mode to the functions listed in Table 31. Note that pin number 143 (A24) has no e q u i va l e n t G P S I f u n c t i o n a n d s h o u l d b e l e f t unconnected when GPSI mode is enabled. GPSI signal functions are described in the pin description section under the GPSI subheading. At the time that GPSI mode is entered, the internal MAC clock is switched from a XTAL1-derived clock to a clock derived from the STDCLK input. The STDCLK input determines the network data rate and therefore must meet frequency and stability specifications.
10 01 11 XX
1 1 1 0
X 0 X 0
XX
0
1
Note that the TSTSHDW bit values are only active when PVALID is TRUE. The GPSI interface is multiplexed through 7 of the upper 8 address bits of the system bus interface. Therefore, applications that require the use of the GPSI interface will be limited to the use of only 24 address bits (A[23] through A[2] plus the byte enables, which decode into two effective address bits). In order to prevent the PCnet-32 controller from interpreting the GPSI signals as address bits during the Software Relocatable Mode and du r in g s lave accesses, the 24-bit Software Relocatable Mode Address 24 mode and the I/O Address Width 24 mode of the PCnet-32 controller must be invoked. Note that if Software Relocatable Mode is invoked, then PVALID must have been set to ZERO, and, therefore, the GPSI
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Table 31. GPSI Pin Configurations
GPSI Function GPSI I/O Type O O I I I I LANCE GPSI Pin TX TENA TCLK CLSN RCLK RX ILACC GPSI Pin TXD RTS TXC CDT RXC RXD PCnet-32/ PCnet-ISA GPSI Pin TXDAT TXEN STDCLK CLSN SRDCLK RXDAT PCnet-32 Pin Number 132 133 134 137 140 141 PCnet-32 Normal Pin Function A31 A30 A29 A28 A26 A25
Transmit Data Transmit Enable Transmit Clock Collision Receive Clock Receive Data
Note that the XTAL1 input must always be driven with a clock source, even if GPSI mode is to be used. It is not necessary for the XTAL1 clock to meet the normal frequency and stability requirements in this case. Any frequency between 8 MHz and 20 MHz is acceptable. However, voltage drive requirements do not change. When GPSI mode is used, XTAL1 must be driven for several reasons: 1. The default pin RESET configuration for the PCnet-32 controller is "AUI port selected," and until GPSI mode is selected, the XTAL1 clock is needed for some internal operations (namely, RESET). 2. The XTAL1 clock drives the EEPROM read operation, regardless of the network mode selected. 3. The XTAL1 clock determines the length of a Reset Register read operation, regardless of the network mode selected (due to the internal RESET caused by the read). Note that if a clock slower than 20 MHz is provided at the XTAL1 input, the time needed for EEPROM read and Reset Register Read operations will increase.
signal LGNT/ HLDA will be passed directly to the daisychain signal LGNTO/HLDAO. In snooze mode, enabled by setting the AWAKE bit in BCR2 and driving the SLEEP pin LOW, the T-MAU receive circuitry will remain enabled even while the SLEEP pin is driven LOW. The LNKST output will also continue to function, indicating a good 10BASE-T link if there are link beat pulses or valid frames present. This LNKST pin can be used to drive an LED and/or external hardware that directly controls the SLEEP pin of the PCnet-32 controller. This configuration effectively wakes the system when there is any activity on the 10BASE-T link. Auto wake mode can be used only if the T-MAU is the selected network port. Link beat pulses are not transmitted during Auto-wake mode. The system bus interface will be floated and inactive during snooze mode. LDEV and the selected interrupt pin will be driven to inactive levels. While in snooze mode, if the PCnet-32 controller is configured for a daisy chain (HOLDI and HLDAO or LREQI and LGNTO signals have been selected with the JTAGSEL pin), then the daisy chain signal LREQI/HOLDI will be passed directly to LREQ/HOLD and the system arbitration signal LGNT/HLDA will be passed directly to the daisy-chain signal LGNTO/HLDAO. If the HOLD output is active when the SLEEP pin is asserted, then the PCnet-32 controller will wait until the HLDA input is asserted. Then the PCnet-32 controller will de-assert the HOLD pin and finally, it will internally enter either the coma or snooze sleep mode. Before the sleep mode is invoked, the PCnet-32 controller will perform an internal S_RESET. This S_RESET operation will not affect the values of the BCR registers. The SLEEP pin should not be asserted during power supply ramp-up. If it is desired that SLEEP be asserted at power up time, then the system must delay the assertion of SLEEP until three BCLK cycles after the completion of a valid pin RESET operation.
Power Savings Modes
The PCnet-32 controller supports two hardware power savings modes. Both are entered by driving the SLEEP pin LOW. In coma mode, the PCnet-32 controller will go into a deep sleep with no means to use the network to automatically wake itself up. Coma mode is enabled when the AWAKE bit in BCR2 is reset. Coma mode is the default power down mode. When coma mode is invoked, the T-MAU circuitry will go into power down mode. The system bus interface will be floated and inactive during coma mode. LDEV and the selected interrupt pin will be driven to inactive levels. While in coma mode, if the PCnet-32 controller is configured for a daisy chain (HOLDI and HLDAO or LREQI and LGNTO signals have been selected with the JTAGSEL pin), then the daisy chain signal LREQI/HOLDI will be passed directly to LREQ/HOLD and the system arbitration
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Software Access
I/O Resources PCnet-32 Controller I/O Resource Mapping The PCnet-32 controller has several I/O resources. These resources use 32 bytes of I/O space that begin at the PCnet-32 controller I/O Base Address. The PCnet-32 controller allows two modes of slave access. Word I/O mode treats all PCnet-32 controller I/O Resources as two-byte entities spaced at two-byte address intervals. Double Word I/O mode treats all PCnet-32 controller I/O Resources as four-byte entities spaced at four-byte address intervals. The selection of WIO or DWIO mode is accomplished by one of two ways: 1. H_RESET function.
Offset (Hex) 0 2 4 8 A C E 10 12 14 16 18 1A 1C 1E
Table 32. Word I/O Mapping
No. of Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Register Address PROM Address PROM Address PROM Address PROM Address PROM Address PROM Address PROM RDP RAP (shared by RDP and BDP) Reset Register BDP Vendor Specific Word Reserved Reserved Reserved
2. The PCnet-32 controller I/O mode setting will default to WIO after H_RESET (i.e. DWIO = 0). 3. Automatic determination of DWIO mode due to double-word I/O write access to offset 10h. DWIO is automatically programmed as active when the system attempts a double word write access to offset 10h of the PCnet-32 controller I/O space. Note that this space corresponds to RDP, regardless of whether DWIO or WIO mode has been programmed. The power up H_RESET value of DWIO will be ZERO, and this value will be maintained until a double word access is performed to PCnet-32 controller I/O space. Therefore, if DWIO mode is desired, it is imperative that the first access to the PCnet-32 controller be a double word write access to offset 10h. Alternatively, if DWIO mode is not desired, then it is imperative that the software never executes a double word write access to offset 10h of the PCnet-32 controller I/O space. Once the DWIO bit has been set to a ONE, only a H_RESET can reset it to a ZERO. The DWIO mode setting is unaffected by S_RESET or the STOP bit. WIO I/O Resource Map When the PCnet-32 controller I/O space is mapped as Word I/O, then the resources that are allotted to the PCnet-32 controller occur on word boundaries that are offset from the PCnet-32 controller I/O Base Address as shown in Table 32.
When PCnet-32 controller I/O space is Word mapped, all I/O resources fall on word boundaries and all I/O resources are word quantities. However, while in Word I/ O mode, address PROM accesses may also be accessed as individual bytes on byte addresses. Attempts to write to any PCnet-32 controller I/O resources (except to offset 10h, RDP) as 32 bit quantities while in Word I/O mode are illegal and may cause unexpected reprogramming of the PCnet-32 controller control registers. Attempts to read from any PCnet-32 controller I/O resources as 32-bit quantities while in Word I/O mode are illegal and will yield undefined values. An attempt to write to offset 10H (RDP) as a 32 bit quantity while in Word I/O mode will cause the PCnet-32 controller to exit WIO mode and immediately thereafter, to enter DWIO mode. Accesses to non-word address boundaries are not allowed while in WIO mode, with the exception of the APROM locations. The PCnet-32 controller may or may not produce an LDEV and a RDY signal in response to such accesses, but data will be undefined. Accesses of non-word quantities to any I/O resource are not allowed while in WIO mode, with the exception of byte reads from the APROM locations. PCnet-32 controller may or may not produce an LDEV and will not produce a RDY signal in response to such accesses, but data will be undefined. The Vendor Specific Word (VSW) is not implemented by the PCnet-32 controller. This particular I/O address is reserved for customer use and will not be used by future AMD Ethernet controller products. If more than
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one Vendor Specific Word is needed, it is suggested that the VSW location should be divided into a VSW Register Address Pointer (VSWRAP) at one location (e.g. VSWRAP at byte location 18h) and a VSW Data Port (VSWDP) at the other location (e.g. VSWDP at byte location 19h). Alternatively, the system may capture RAP data accesses in parallel with the PCnet-32 controller and therefore share the PCnet-32 controller RAP to allow expanded VSW space. PCnet-32 controller will not respond to access to the VSW I/O address. DWIO I/O Resource Map When the PCnet-32 controller I/O space is mapped as Double Word I/O, then all of the resources that are allotted to the PCnet-32 controller occur on double word boundaries that are offset from the PCnet-32 controller I/O Base Address as shown in Table 33.
Table 33. Double Word I/O Mapping
Offset (Hex) 0 4 8 C 10 14 18 1C No. of Bytes 4 4 4 4 4 4 4 4 Register Address PROM Address PROM Address PROM Address PROM RDP RAP (shared by RDP and BDP) Reset Register BDP
undefined, except for the APROM locations and CSR88. DWIO mode is exited by asserting the RESET pin. Assertion of S_RESET or setting the STOP bit of CSR0 will have no effect on the DWIO mode setting. I/O Space Comments The following statements apply to both WIO and DWIO mapping: The RAP is shared by the RDP and the BDP. The PCnet-32 controller does not respond to any addresses outside of the offset range 0h-17h when DWIO = 0 or 0h-1F when DWIO = 1. I/O offsets 18h through 1Fh are not used by the PCnet-32 controller when programmed for DWIO = 0 mode. Locations 1Ah through 1Fh are reserved for future AMD use and therefore should not be implemented by the user if upward compatibility to future AMD devices is desired. Note that Address PROM accesses do not directly access the EEPROM, but are redirected to a set of shadow registers on board the PCnet-32 controller that contain a copy of the EEPROM contents that was obtained dur ing the automatic EEPRO M read operation that follows the RESET operation. PCnet-32 Controller I/O Base Address The I/O Base Address Registers (BCR16 and BCR17) will reflect the current value of the base of the PCnet-32 controller I/O address space. BCR16 contains the lower 16 bits of the 32-bit I/O base address for the PCnet-32 controller. BCR17 contains the upper 16 bits of the 32-bit I/O base address for the PCnet-32 controller. This set of registers is both readable and writable by the host. The value contained in these registers is affected through three means: 1. Immediately following the H_RESET operation, the I/O Base Address will be determined by the EEPROM read operation. During this operation, the I/O Base Address register will become programmed with the value of the I/O Base Address field of the EEPROM. 2. If no EEPROM exists, or if an error is detected in the EEPROM data, then the PCnet-32 controller will enter Software Relocatable Mode. While in this mode, the PCnet-32 controller will not respond to any I/O accesses directly. However, the PCnet-32 controller will snoop accesses on the system bus. When the PCnet-32 controller detects a specific sequence of four write accesses to I/O address 378h, then the PCnet-32 controller will assume that the software is attempting to relocate the PCnet-32 controller. On eight subsequent write accesses to I/O address 378h, the PCnet-32 controller will accept the data on the bus as a new I/O Base Address and other programming infor-
When PCnet-32 controller I/O space is Double Wordmapped, all I/O resources fall on double word boundaries. Address PROM resources are double word quantities in DWIO mode. RDP, RAP and BDP contain only two bytes of valid data. The other two bytes of these resources are reserved for future use. The reserved bits must be written as zeros, and when read, are considered undefined. Accesses to non-double word address boundaries are not allowed while in DWIO mode. The PCnet-32 controller may or may not produce an LDEV and a RDY signal in response to such accesses, but data will be undefined. Accesses of less than 4 bytes to any I/O resource are not allowed while in DWIO mode (i.e. PCnet-32 controller will not respond to such accesses. PCnet-32 controller will not produce an LDEV and a RDY signal in response to such accesses), but data will be undefined. A double word write access to the RDP offset of 10h will automatically program DWIO mode. Note that in all cases when I/O resource width is defined as 32 bits, the upper 16 bits of the I/O resource is reserved and written as ZEROs and read as
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mation, and it will leave Software Relocatable Mode. At this point, the PCnet-32 controller will begin responding to I/O accesses directly. While the PCnet-32 controller is in software relocatable mode, if the LED2 pin is pulled LOW, then the SRMA24 mode is entered and only the lower 24 bits of address are matched to 378h. 3. The I/O Base Address Registers may be directly written to, provided that the PCnet-32 controller is not currently in the Software Relocatable Mode. Software Relocation of I/O Resources In order to allow for jumperless Ethernet implementations, the I/O Base Address register value will be automatically altered by the PCnet-32 controller during an EEPROM read operation. In this case, the value of the I/O Base Address for the PCnet-32 controller will be directly dependent upon the value of the BCR16 and BCR17 fields that are stored in the EEPROM. If no EEPROM exists and an EEPROM read is attempted, then the PCnet-32 controller will enter Software Relocatable Mode. Software Relocatable Mode While in Software Relocatable Mode, the PCnet-32 controller will not respond to any access on the system bus. However, the PCnet-32 controller will snoop any I/ O write accesses that may be present. The PCnet-32 controller will watch for a specific sequence of accesses in order to determine a value for the I/O Base Address Registers. Specifically, the PCnet-32 controller will wait for a sequence of 12 uninterrupted byte-write accesses to I/O address 378h. The 12 byte-write accesses must occur without intervening I/O accesses to other locations, and they must contain the data in the order shown in Table 34. BE0 is required to be active during all Software Relocatable Mode snoop accesses. BE3-BE1 may have any value during Software Relocatable Mode snoop accesses.
Table 34. I/O Base Address Write Sequence in SRM
Access No. I/O Address (Hex) 0000 0378 0000 0378 0000 0378 0000 0378 0000 0378 0000 0378 0000 0378 0000 0378 0000 0378 0000 0378 0000 0378 D[7:0]* (Hex) 41 4D 44 01 IOBASEL[7:0] IOBASEL[15:8] IOBASEU[15:8] BCR2[7:0] BCR2[15:8] BCR21[7:0] BCR21[15:8] ASCII Inter- pretation A M D NA NA NA NA NA NA NA NA
1 2 3 4 5 6 8 9 10 11 12
*Note that D[31:8] are don't care, since the accesses are required to one byte in width. Immediately following the 12th write access in the sequence, the PCnet-32 controller will leave Software Relocatable Mode, and it will then respond to I/O accesses to the 32 bytes of I/O space that begins at the I/O Base Address location. Note that in Figure 33 (Software Relocatable Mode Snoop Accesses), the data that is accepted by the PCnet-32 controller will always be the data that is presented during the first T2 cycle, regardless of the state of the RDYRTN input. Since the PCnet-32 controller will not respond to the Software Relocatable Mode snoop accesses, some other device must drive the RDYRTN signal during these accesses. In a typical PC environment, these I/O accesses will be directed toward the data port of a parallel port. Therefore, the RDYRTN will typically be generated by the parallel port controller. In systems in which the parallel port device does not exist, or is at a different location, the 378h accesses will go unclaimed by any device on the local bus or on the expansion bus. In this case, the chipset will typically terminate the access by providing the RDYRTN signal after some access-time-out counter has elapsed.
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PCnet-32 controller latches snoop data on this edge
PCnet-32 controller latches snoop data on this edge
PCnet-32 controller latches snoop data on this edge
T1 BCLK
T2
T2
T1
T2
T1
T2
T2
T2
Ti
T1
T2
ADS A4 A31, M/IO, D/C
I/O Address 378h
I/O Address 378h
I/O Address 378h
I/O Address 378h
W/R A2 A3, BE1 BE3 BE0
I/O Address 378h
I/O Address 378h
I/O Address 378h
I/O Address 378h
RDYRTN
BRDY
BLAST
SRM Data SRM Data SRM Data
D0 D7
D8 D31
Don't Care
18219-40
Figure 33. Software Relocatable Mode Snoop Cycles
The I/O Base Address register value may be altered by a direct write to BCR16 and BCR17 by the host. Slave accesses to the PCnet-32 controller should not be performed until both BCR16 and BCR17 have been written with new values. An intermediate I/O Base address will be created when only one of the two registers has been written. Therefore, this method of I/O Base address reassignment is not recommended. I/O Register Access All I/O resources are accessed with similar I/O bus cycles.
I/O accesses to the PCnet-32 controller begin with a valid ADS strobe and an address on the A[31:2] lines that falls within the I/O space of the PCnet-32 controller. The PCnet-32 controller I/O space will be determined by the I/O Base Address Registers. EEPROM read operations will determine the value of the I/O Base Address Registers. The PCnet-32 controller will respond to an access to its I/O space by asserting the LDEV signal and eventually, by asserting the RDY signal. Typical I/O access times are 6 or 7 BCLK periods. The
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exact number of clock cycles for any particular access will depend upon the relative phases of the signal on the BCLK pin and the internal clock that is used to drive the PCnet-32 controller buffer management unit. Since the PCnet-32 controller buffer management unit operates on a clock that is a /2 version of the interface clock, it possible for the buffer management unit to introduce one or more BCLK wait delays to allow for
synchronization of the two state machines before proceeding
RDP Access (CSR Register Space) RDP = Register Data Port. The RDP is used with the RAP to gain access to any of the PCnet-32 controller CSR locations. Access to any of the CSR locations of the PCnet-32 controller is perfor med thr ough the PCnet-32 controller's Register Data Port (RDP). In order to access a particular CSR location, the Register Address Port (RAP) should first be written with the appropriate CSR address. The RDP now points to the selected CSR. A read of the RDP will yield the selected CSR's data. A write to the RDP will write to the selected CSR. When programmed for WIO mode, the RDP has a width of 16 bits, hence, all CSR locations have 16 bits of width. Note that when accessing RDP, the upper two bytes of the data bus will be undefined since the byte masks will not be active for those bytes. If DWIO mode has been invoked, then the RDP has a width of 32 bits, hence, all CSR locations have 32 bits of width and the upper two bytes of the data bus will be active, as indicated by the byte mask. In this case, note that the upper 16 bits of all CSR locations (except CSR88) are reserved and written as zeros and read as undefined values. Therefore, during RDP write operations in DWIO mode, the upper 16 bits of all CSR locations should be written as ZEROs. RAP Access RAP = Register Address Port. The RAP is used with the RDP and with the BDP to gain access to any of the CSR and BCR register locations, respectively. The RAP contains the address pointer that will be used by an access to either the RDP or BDP. Therefore, it is necessary to set the RAP value before accessing a specific CSR or BCR location. Once the RAP has been written with a value, the RAP value remains unchanged until another RAP write occurs, or until an H_RESET or S_RESET occurs. RAP is set to all zeros when an H_RESET or S_RESET occurs. RAP is unaffected by the STOP bit. When programmed for WIO mode, the RAP has a width of 16 bits. Note that when accessing RAP, the lower two bytes of the data bus will be undefined since the byte masks will not be active for those bytes When programmed for DWIO mode, the RAP has a width of 32 bits. In DWIO mode, the upper 16 bits of the RAP are reserved and written as zeros and read as undefined. These bits should be written as zeros. BDP Access (BCR Register Space) BDP = Bus Configuration Register Data Port. The BDP is used with the RAP to gain access to any of the PCnet-32 controller BCR locations. Access to any of the BCR locations of the PCnet-32 controller is perfor med thr ough the PCnet-32
with the access. The PCnet-32 buffer management unit uses BCLK /2, so the maximum number of BCLK cycles needed to synchronize the BIU and buffer management units is one BCLK period. APROM Access The APROM space is a convenient place to store the value of the IEEE station address. This space is automatically loaded from the serial EEPROM, if an EEPROM is present. Its contents have no effect on the operation of the controller. The software must copy the station address from the APROM space to the Initialization Block or to CSR12-CSR14 in order for the receiver to accept unicast frames directed to this station. When programmed for WIO mode, any byte or word address from an offset of 0h to an offset of Fh may be read. An appropriate byte or word of APROM contents will be delivered by the PCnet-32 controller in response to accesses that fall within the APROM range of 0h to Fh. When programmed for DWIO mode, only double word addresses from an offset of 0h to an offset of Fh may be read. An appropriate double word of APROM contents will be delivered in response to accesses that fall within the APROM range of 0h to Fh. Reads of non-double-word quantities are not allowed in DWIO mode, even though such an access may be properly aligned to a double word address boundary. Write access to any of the APROM locations is allowed, but only 4 bytes on double-word boundaries in DWIO mode or 2 bytes on word boundaries in WIO mode. The IESRWE bit (see BCR2) must be set in order to enable such a write. Only the PCnet-32 controller on-board IEEE Shadow registers are modified by writes to APROM locations. The EEPROM is unaffected by writes to APROM locations. Note that the APROM locations occupy 16 bytes of space, yet the IEEE station address requirement is for 6 bytes. The 6 bytes of IEEE station address occupy the first 6 locations of the APROM space. The next six bytes are reserved. Bytes 12 and 13 should match the value of the checksum of bytes 1 through 11 and 14 and 15. Bytes 14 and 15 should each be ASCII "W" (57 h) if compatibility to AMD driver software is desired.
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controller's BCR Data Port (BDP). In order to access a particular BCR location, the Register Address Port (RAP) should first be written with the appropriate BCR address. The BDP now points to the selected BCR. A read of the BDP will yield the selected BCR's data. A write to the BDP will write to the selected BCR. When programmed for WIO mode, the BDP has a width of 16 bits, hence, all BCR locations have 16 bits of width in WIO mode. Note that when operating in WIO mode, the upper two bytes of the data bus will be undefined since the byte mask will not be active for those bytes. If DWIO mode has been invoked, then the BDP has a width of 32 bits, hence, all BCR locations have 32 bits of width and the upper two bytes of the data bus will be active, as indicated by the byte mask. In this case, note that the upper 16 bits of all BCR locations are reserved and written as zeros and read as undefined. Therefore, during BDP write operations in DWIO mode, the upper 16 bits of all BCR locations should be written as zeros. Reset Register (S_RESET) A read of the reset register creates an internal S_RESET pulse in the PCnet-32 controller. This read access cycle must be 16 bits wide in WIO mode and 32 bits wide in DWIO mode. The internal S_RESET pulse that is generated by this access is different from both the assertion of the hardware RESET pin (H_RESET) and from the assertion of the software STOP bit. Specifically, the Reset register's S_RESET will be the equivalent of the asser tion of the RESET pin (H_RESET) asser tion for all CSR locations, but S_RESET will have no effect at all on the BCR locations, and S_RESET will not cause a de-assertion of the HOLD pin. The NE2100 LANCE based family of Ethernet cards requires that a write access to the reset register follows each read access to the reset register. The PCnet-32 controller does not have a similar requirement. The write access is not required but it does not have any harmful effects. Write accesses to the reset register will have no effect on the PCnet-32 controller.
Note that a read of the Reset register will take longer than the normal I/O access time of the PCnet-32 controller. This is because an internal S_RESET pulse will be generated due to this access, and the access will not be allowed to complete on the system bus until the internal S_RESET operation has been completed. This is to avoid the problem of allowing a new I/O access to proceed while the S_RESET operation has not yet completed, which would result in erroneous data being returned by (or written into) the PCnet-32 controller. The length of a read of the Reset register can be as long as 128 BCLK cycles when Am386 mode has been selected and 64 BCLK cycles when Am486 mode or VESA VL-Bus mode has been selected. Note that a read of the Reset register will not cause a de-assertion of the HOLD signal, if it happens to be active at the time of the read to the reset register. The HOLD signal will remain active until the HLDA signal is synchronously sampled as asserted. Following the read of the RESET register, on the next clock cycle after the HLDA signal is synchronously sampled as asserted, the PCnet-32 controller will de-assert the HOLD signal). No bus master accesses will have been performed during this brief bus ownership period. Note that this behavior differs from that which occurs following the assertion of a minimum-width pulse on the RESET pin (H_RESET). A RESET pin assertion will cause the HOLD signal to de-assert within six clock cycles following the assertion. In the RESET pin case, the PCnet-32 controller will not wait for the assertion of the HLDA signal before de-asserting the HOLD signal. Vendor Specific Word This I/O offset is reserved for use by the system designer. The PCnet-32 controller will not respond to accesses directed toward this offset. Reserved I/O Space These locations are reserved for future use by AMD. The PCnet-32 controller does not respond to accesses directed toward these locations, but future AMD products that are intended to be upward compatible with the PCnet-32 controller may decode accesses to these locations. Therefore, the system designer may not utilize these I/O locations.
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Hardware Access
PCnet-32 Controller Master Accesses The particular signals involved in a PCnet-32 controller bus master transfer depends upon the bus mode that has been selected. There are two bus modes to choose from. They are: s Am486 32-bit mode s VESA VL-Bus mode Complete descriptions of the signals involved in bus master transactions for each mode may be found in the pin description section of this document. Timing diagrams for master accesses may be found in the block description section for the Bus Interface Unit. This section simply lists the types of master accesses that will be performed by the PCnet-32 controller with respect to data size and address information. The PCnet-32 controller will support master accesses only to 32-bit peripherals in Am486 environments. The PCnet-32 controller does not support master accesses to 16-bit peripherals in the 486 local bus mode. The PCnet-32 controller will support master accesses to either 32-bit or 16-bit peripherals in VESA VL-Bus m o de. S u p p o r t o f ma s t e r a c c e s s e s to 1 6 - b i t peripherals in VESA VL-Bus mode is provided through the LBS16 input pin. The PCnet-32 controller is not compatible with 8-bit systems, since there is no mode that suppor ts PCnet-32 controller accesses to 8-bit peripherals. Table 35 describes all possible bus master accesses that the PCnet-32 controller will perform. The rightmost column lists all operations that may execute the given access.
4-Byte Write
Table 35. Master Accesses Access
4-Byte Read
R/W
RD
BE3-BE0
0000
Possible Instance
Descriptor Read or Initialization Block Read or Transmit Data Buffer Read Descriptor Write or Receive Data Buffer Write Receive Data Buffer Write Receive Data Buffer Write Receive Data Buffer Write Receive Data Buffer Write Receive Data Buffer Write Receive Data Buffer Write Receive Data Buffer Write Receive Data Buffer Write Descriptor Write or Receive Data Buffer Write
WR
0000
3-Byte Write
WR
1000
3-Byte Write
WR
0001
2-Byte Write
WR
1100
2-Byte Write
WR
1001*
2-Byte Write
WR
0011
1-Byte Write
WR
1110
1-Byte Write
WR
1101*
1-Byte Write
WR
1011*
1-Byte Write
WR
0111
*Cases marked with an asterisk represent extreme boundary conditions that are the result of programming one- and two-byte buffer sizes, and therefore will not be seen under normal circumstances. Note that all PCnet-32 controller master read operations will always activate all byte enables. (Note the exception, when LBS16 has been asserted in VLBus mode, requiring a second access. In all LBS16 cases, the second access (if required) will have BE1 and BE0 disabled. Therefore, no one-, two- or threebyte read operations are indicated in the table. In the instance where a transmit buffer pointer address begins on a non-double-word boundary, the pointer will be truncated to the next double-word boundary address that lies below the given pointer address and the first read access from the transmit buffer will be indicated on the byte enable signals as a four-byte read from this address. Any data from byte lanes that lie outside of the boundary indicated by the buffer pointer will be discarded inside of the PCnet-32 controller.
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Similarly, if the end of a transmit buffer occurs on a nondouble-word boundary, then all byte lanes will be indicated as active by the byte enable signals, and any data from byte lanes that lie outside of the boundary indicated by the buffer pointer will be discarded inside of the PCnet-32 controller. Slave Access to I/O Resources The PCnet-32 controller is a 32-bit peripheral device on the system bus. However, the width of individual software resources on board the PCnet-32 controller may be either 16-bits or 32-bits. The PCnet-32 controller I/O resource widths are determined by the value of the DWIO bit (BCR 18, bit 7) as indicated in Table 36. Note that when I/O resource width is defined as 32 bits (DWIO mode), the upper 16 bits of the I/O resource is
reserved and written as ZEROs and read as undefined, except for the APROM locations. The APROM locations are the only I/O resources for which all 32 bits will have defined values. However, this is true only when the PCnet-32 controller is in DWIO mode. Configuring the PCnet-32 controller for DWIO mode is accomplished whenever there is any attempt to perform a 32-bit write access to the RDP location (offset 10h). See the DWIO section for more details. Table 37 describes all possible bus slave accesses that may be directed toward the PCnet-32 controller. (i.e. the PCnet-32 controller is the slave device during the transfer.) The four byte columns (D31-D24, D23-D16, D15-D8, D7-D0) indicate the value on the data bus during the access.
Table 36. I/O Resource Access
DWIO Setting DWIO = 0 DWIO = 1 PCnet-32 Controller I/O Resource Width 16-bit 32-bit Example Application Existing PCnet-ISA driver that assumes 16-bit I/O mapping and 16-bit resource widths New drivers written specifically for the PCnet-32 controller
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Table 37. Slave Accesses R/W
RD RD RD RD RD RD RD WR WR WR
BE3 - BE0
0000 1100 0011 1110 1101 1011 0111 0000 1100 0011
D31-D24
Data Undef Data Undef Undef Undef Data Data Undef Data
D23-D16
Data Undef Data Undef Undef Data Undef Data Undef Data
D15-D8
Data Data Copy Undef Data Undef Copy Data Data Undef
D7-D0
Data Data Copy Data Undef Copy Undef Data Data Undef
Comments
Double word access to double word address, e.g. 300, 30C, 310 (DWIO mode only) WIO Mode Only: Word access to even word address, e.g. 300, 30C, 310 WIO Mode Only: Word access to odd word address, e.g. 302, 30E, 312 WIO Mode APROM Read Only: Byte access to lower byte of even word address, e.g. 300, 304 WIO Mode APROM Read Only: Byte access to upper byte of even word address, e.g. 301, 305 WIO Mode APROM Read Only: Byte access to lower byte of odd word address, e.g. 302, 306 WIO Mode APROM Read Only: Byte access to upper byte of odd word address, e.g. 303, 307 Double word access to double word address, e.g. 300, 30C, 310 (DWIO mode only) WIO Mode Only: Word access to even word address, e.g. 300, 30C, 310 WIO Mode Only: Word access to odd word address, e.g. 302, 30E, 312
Data = indicates the position of the active bytes. Copy = indicates the positions of copies of the active bytes. Undef = indicates byte locations that are undefined during the transfer. EEPROM Microwire Access The PCnet-32 controller contains a built-in capability for reading and writing to an external EEPROM. This built-in capability consists of a microwire interface for direct connection to a microwire compatible EEPROM, an automatic EEPROM read feature, and a userprogrammable register that allows direct access to the microwire interface pins. Automatic EEPROM Read Operation Shortly after the de-assertion of the RESET pin, the PCnet-32 controller will read the contents of the EEPROM that is attached to the microwire interface.The automatic EEPROM read begins with EECS being asserted approximately 2.5 EESK periods ( 2.5 ) following the de-assertion of the RESET pin. t42 Because of this automatic-read capability of the PCnet-32 controller, an EEPROM can be used to program many of the features of the PCnet-32 controller at power-up, allowing system-dependent configuration information to be stored in the hardware, instead of inside of operating code. PCnet-32 controller interrupt pins will be floated during H_RESET and will remain floated until either the EEPROM has been
successfully read, or, following an EEPROM read failure, a Software Relocatable Mode sequence has been successfully executed. If an EEPROM exists on the microwire interface, the PCnet-32 controller will read the EEPROM contents at the end of the H_RESET operation. The EEPROM contents will be serially shifted into a temporary register and then sent to various register locations on board the PCnet-32 controller. System bus interaction will not occur during the EEPROM read operation after H_RESET, since H_RESET will put the PCnet-32 controller into a state that will not recognize any I/O accesses and the PCnet-32 controller will not yet be at an operating point that requires it to request the bus for bus mastering. Thirty-four bytes of the EEPROM are set aside for PCnet-32 configuration programming and 2 bytes of the EEPROM are set aside for user programming of logic that is external to the PCnet-32 controller and may or may not be per tinent to the operation of the PCnet-32 controller within the system. The user may gain access to the EEPROM data by snooping the PCnet-32 controller automatic read operation. Logic may be attached to the EEPROM interface to snoop the entire EEPROM read operation using the microwire signals directly, or a simpler scheme may be invoked by taking advantage of an additional signal provided by the PCnet-32 controller (i.e. the SHFBUSY signal). A checksum verification is performed on the data that is read from the EEPROM. If the checksum verification
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of the EEPROM data fails, then at the end of the EEPROM read sequence, the PCnet-32 controller will force all EEPROM-programmable register locations back to their H_RESET default values and then the PCnet-32 controller will enter Software Relocatable Mode. The 8-bit checksum for the entire 36 bytes of the EEPROM should be FFh. In the event of a checksum failure, Software Relocatable Mode is entered (PCnet-32 controller begins snooping for a 12-byte sequence) within 1 EESK period following the de1 assertion of EECS ( t ).
42
If the absence of an EEPROM has been signaled by the EESK/LED1/SFBD pin at the time of the automatic read operation, then the PCnet-32 controller will recognize this condition and will abort the automatic read operation and reset both the PREAD and PVALID bits in BCR19. At this point, the PCnet-32 controller will enter the Software Relocatable Mode, and the EEPROM-programmable registers will be assigned their H_RESET default values. Software Relocatable Mode is entered (PCnet-32 controller begins snooping for 12-byte sequence) within 2.5 EESK periods ( 2.5 ) t42 following the de-assertion of the RESET pin when absence of an EEPROM is signalled by the EESK/LEDI SFBD pin. If the user wishes to modify any of the configuration bits that are contained in the EEPROM, then the 7 command, data and status bits of BCR19 can be used to write to the EEPROM. After writing to the EEPROM, the host should set the PREAD bit of BCR19. This action forces a PCnet-32 controller re-read of the EEPROM so that the new EEPROM contents will be loaded into the EEPROM-programmable registers on board the PCnet-32 controller. (The EEPROMprogrammable registers may also be reprogrammed directly, but only information that is stored in the EEPROM will be preserved at system power-down.) When the PREAD bit of BCR19 is set, it will cause the PCnet-32 controller to ignore further accesses on the system interface bus until the completion of the EEPROM read operation. EEPROM Auto-Detection The PCnet-32 controller uses the EESK/LED1/SFBD pin to determine if an EEPROM is present in the system. At all rising BCLK edges during the assertion of the RESET pin, the PCnet-32 controller will sample the value of the EESK/LED1/SFBD pin. If the sampled value is a ONE, then the PCnet-32 controller assumes that an EEPROM is present, and the EEPROM read operation begins shortly after the RESET pin is deasserted. If the sampled value of EESK/LED1/SFBD is
a ZERO, then the PCnet-32 controller assumes that an external pull-down device is holding the EESK/LED1/ SFBD pin low, and therefore, there is no EEPROM in the system. In this case, the PCnet-32 controller will enter Software Relocatable Mode. Note that if the designer creates a system that contains an LED circuit on the EESK/LED1/SFBD pin but has no EEPROM present, then the EEPROM auto-detection function will incorrectly conclude that an EEPROM is present in the system. However, this will not pose a problem for the PCnet-32 controller, since it will recognize the lack of an EEPROM at the end of the read operation, when the checksum verification fails. At this point, the PCnet-32 controller will enter Software Relocatable Mode. The real intention of the EEPROM auto-detection feature is to allow a user to preempt a "good EEPROM" by temporarily resistively shorting the EESK/LED1/SFBD pin to ground. This may need to be done if an add-in card containing the PCnet-32 controller and its EEPROM has been programmed in one system and then later moved to a different system without also moving configuration information that indicates the I/O Base address of the card. The card would power up in the second system with an unknown I/O Base address if the configuration information were not carried with the card to the new system. By allowing the EESK/ LED1/SFBD pin to be temporarily resistively shorted to ground, the PCnet-32 controller is fooled into believing that the EEPROM does not exist, and it will enter Software Relocatable Mode. This allows the new system to reconfigure the I/O Base address of the PCnet-32 controller to a location that is compatible to the parameters of the new system. This information will then be written into the EEPROM by a configuration utility through the EEPROM access port (BCR19), in spite of the fact that the PCnet-32 controller believes that there is no EEPROM. The resistive short to ground may now be removed, and the next power-up of the system will place the PCnet-32 controller into a I/O location that is known by this system. When the PREAD bit of BCR19 is set, an EEPROM read operation will be performed, regardless of the value of the EESK/ LED1/SFBD pin. Note that the H_RESETgenerated EEPROM read operation always obeys the EESK/ LED1/SFBD indication. Table 38 indicates the possible combinations of EEDET and the existence of an EEPROM and the resulting operations that are possible on the EEPROM microwire interface. Note that the EEDET value (BCR19, bit 3) is determined from EESK/LED1/SFBD pin setting, and it may be set even though there is no EEPROM present.
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Table 38. Effect of EEDET on EEPROM Operation
EEDET Value (BCR19[3]) 0 EEPROM Connected? No Result if PREAD is set to ONE EEPROM read operation is attempted. Entire read sequence will occur, checksum failure will result, PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum operation will pass, PVALID is set to ONE. EEPROM read operation is attempted. Entire read sequence will occur, checksum failure will result, PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum operation will pass, PVALID is set to ONE. Result of Automatic EEPROM Read Operation Following H_RESET First TWO EESK clock cycles are generated, then EEPROM read operation is aborted and PVALID is reset to ZERO. First TWO EESK clock cycles are generated, then EEPROM read operation is aborted and PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum failure will result, PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum operation will pass, PVALID is set to ONE.
0
Yes
1
No
1
Yes
Systems Without an EEPROM Some systems may be able to save the cost of an EEPROM by storing the ISO 8802-3 (IEEE/ANSI 802.3) station address and other configuration information somewhere else in the system. For such a system, a two step process is required. The first step will get the PCnet-32 controller into its nor mal operating mode within the system. The second step will load the IEEE station address. The designer has several choices: 1) If the LED1 and SFBD functions are not needed in the system, then the system designer may connect the EESK/LED1/SFBD pin to a resistive pull-down device. This will indicate to the EEPROM auto-detection function that no EEPROM is present, and the PCnet-32 controller will use Software Relocatable Mode to acquire its I/O Base Address and other configuration information (See the section on Software Relocatable Mode). 2) If either of the LED1 or SFBD functions is needed in the system, then the system designer will connect the EESK/LED1/SFBD pin to a resistive pull-up device and the EEPROM auto-detection function will incorrectly conclude that an EEPROM is present in the system. However, this will not pose a problem for the PCnet-32 controller, since it will recognize the lack of an EEPROM at the end of the read operation, when the checksum verification fails. At this point, the PCnet-32 controller into the Software Relocatable Mode to acquire its I/O Base Address and other configuration
information (See the section on Software Relocatable Mode). In either case, following the execution of Software Relocatable Mode, additional information, including the ISO 8802-3 (IEEE/ANSI 802.3) station address, may be loaded into the PCnet-32 controller. Note that the IESRWE bit (bit 8 of BCR2) must be set before the PCnet-32 controller will accept writes to the APROM offsets within the PCnet-32 controller I/O resources map. Startup code in the system BIOS can perform the Software Relocatable Mode accesses, the IESRWE bit write, and the APROM writes. If compatibility to existing driver code is desired, then it is not recommended that the ISO 8802-3 (IEEE/ANSI 802.3) station address be loaded into the Initialization Block structure in memory instead of the APROM locations, since existing code typically expects to find the ISO 8802-3 (IEEE/ANSI 802.3) station address at the APROM offsets from the PCnet-32 controller I/O Base Address. Direct Access to the Microwire Interface The user may directly access the microwire por t through the EEPROM register, BCR19. This register contains bits that can be used to control the microwire interface pins. By performing an appropriate sequence of I/O accesses to BCR19, the user can effectively write to and read from the EEPROM. This feature may be used by a system configuration utility to program hardware configuration information into the EEPROM.
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EEPROM-Programmable Registers The following registers contain configuration information that will be programmed automatically during the EEPROM read operation:
1) I/O offsets 0h-Fh 2) BCR2 3) BCR16 4) BCR17 5) BCR18 6) BCR21 Address PROM locations Miscellaneous Configuration register I/O Base Address Lower I/O Base Address Upper Burst Size and Bus Control Register Interrupt Control Register
EEPROM programmable register will be set to default H_RESET values. At this point, the PCnet-32 controller will enter Software Relocatable Mode. Note that accesses to the Address PROM I/O locations do not directly access the Address EEPROM itself. Instead, these accesses are routed to a set of "shadow" registers on board the PCnet-32 controller that are loaded with a copy of the EEPROM contents during the automatic read operation that immediately follows the H_RESET operation. EEPROM MAP The automatic EEPROM read operation will access 18 words (i.e. 36 bytes) of the EEPROM. The format of the EEPROM contents is shown in Table 39, beginning with the byte that resides at the lowest EEPROM address.
If the PREAD bit (BCR19) is reset to ZERO and the
PVALID bit (BCR19) is reset to ZERO, then the EEPROM read has experienced a failure and the contents of the
Table 39. EEPROM Content EEPROM Word Addr
0 (Lowest Address)
EEPROM Contents Byte Addr Byte Addr
1
MSB (Most Significant Byte)
2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3) station physical address for this node
Byte Addr
0
LSB (Lease Significant Byte)
First byte of the ISO 8802-3 (IEEE/ANSI 802.3) station physical address for this node, where first byte refers to the first byte to appear on the 802.3 medium 3rd byte of the node address 5th byte of the node address Reserved location: must be 00h Driver IRQ: Must be programmed to the system IRQ channel number being used if AMD drivers are used. User programmable space LSB of two-byte checksum, which is the sum of bytes 0-B and bytes E and F Must be ASCII "W" (57h) if compatibility to AMD driver software is desired BCR16[7:0] (I/O Base Address Lower) BCR17[7:0] (I/O Base Address Upper) BCR18[7:0] (Burst Size and Bus Control) BCR2[7:0] (Miscellaneous configuration) BCR21[7:0] (Interrupt Control) Reserved location: must be 00h Reserved location: must be 00h Reserved location: must be 00h
1 2 3 4
3 5 7 9
4th byte of the node address 6th byte of the node address Reserved location: must be 00h Hardware ID: must be 10h if compatibility to AMD drivers is desired User programmable space MSB of two-byte checksum, which is the sum of bytes 0-B and bytes E and F Must be ASCII "W" (57h) if compatibility to AMD driver software is desired BCR16[15:8] (I/O Base Address Lower) BCR17[15:8] (I/O Base Address Upper) BCR18[15:8] (Burst Size and Bus Control) BCR2[15:8] (Miscellaneous configuration) BCR21[15:8] (Interrupt Control) Reserved location: must be 00h Reserved location: must be 00h checksum adjust byte for the first 36 bytes of the EEPROM contents; checksum of the first 36 bytes of the EEPROM should total to FFh Reserved location: must be 00h User programmable byte locations
2 4 6 8
5 6 7 8 9 A B C D E F
B D F 11 13 15 17 19 1B 1D 1F
A C E 10 12 14 16 18 1A 1C 1E
10 11
21 23
20 22
Reserved location: must be 00h User programmable byte locations
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Note that the first bit out of any WORD location in the EEPROM is treated as the MSB of the register that is being programmed. For example, the first bit out of EEPROM WORD location 08h will be written into BCR16[15], the second bit out of EEPROM WORD location 08h will be written into BCR16[14], etc. Th ere ar e two c hecks um loca ti ons withi n th e EEPROM. The first is required for the EEPROM address. This checksum will be used by AMD driver software to verify that the ISO 8802-3 (IEEE/ANSI 802.3) station address has not been corrupted. The value of bytes C and D should match the 16-bit sum of bytes 0 through B and E and F. The second checksum location "byte 1F " is not a checksum total, but is, instead, a checksum adjustment. The value of this byte should be such that the total 8-bit checksum for the entire 36 bytes of EEPROM data equals the value FFh. The checksum adjust byte is needed by the PCnet-32 controller in order to verify that the EEPROM contents have not been corrupted. Byte address 8h of the EEPROM map contains the driver IRQ field. The content of this field is used by AMD drivers to program the interrupt channel being used by the PCnet-32. Note that the PCnet-32 interrupt pin selection is NOT effected by this field. The interrupt pin selection is controlled only by the appropriate bits in BCR21. The system interrupt channel associated with each of the PCnet-32 INTR pins is application-dependent. AMD drivers utilize byte location 8h of the EEPROM to resolve this dependency.
EEPROM-Programming of System Logic When the user has shareable hardware resources in the system and wishes to have these resources programmed at power up, the user may desire to take advantage of the extra space in the EEPROM that is used to configure the PCnet-32 controller in order to store the additional configuration information. The PCnet-32 controller provides a convenient means of access for the user who wishes to utilize this space. The schematic in Figure 34 illustrates an example of logic that is used to generate static control signals for some programmable features of the system, where the programming information is stored on board the PCnet-32 controller's EEPROM and the logic is to be automatically programmed after RESET. Note that the EECS signal pulses low during the EEPROM read operation and is therefore unsuitable for use as a gate signal for the programmable logic outputs. PCnet-32 controller provides an additional signal, SHFBUSY, which will remain active HIGH during the entire EEPROM read operation. This signal will therefore be suitable for use as the gate of the programmable logic outputs as shown in the diagram. Note that since most of the EEPROM microwire interface signals are multiplexed with other PCnet-32 controller functions, it is necessary for the SHFBUSY pin to enable the shift path of the programmable logic, otherwise the shift path would become active when the EESK and EEDO functions were operating as their alternate functions.
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EEDI EEDO
EEDI EEDO EECS EESK
PCnet-32 Controller
EECS EESK SHFBUSY
EEPROM (93LC46)
RESET RESET
FFR
D EN CK R Q
FFR
D EN CK R Q
FFR
D EN CK R Q
...up to 16 bits
RESET
OUT1
OUT2
OUT3
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Figure 34. Programming System Logic Through the PCnet-32 EEPROM Read Operation
SHFBUSY will be HIGH for the entire EEPROM read operation, and therefore all EEPROM contents will have been shifted through the external logic before it settles on its final, programmed value. If the EEPROM checksum verification fails, then the EEPROM contents are assumed to be invalid, and the SHFBUSY signal will remain HIGH after the completion of the EEPROM read operation. This action will prevent incorrect system logic values from being driven into the system. If the EEPROM checksum verification passes, then the EEPROM contents are assumed to be valid, and the SHFBUSY signal will return to a LOW state after the completion of the EEPROM read operation.
matic pad field insertion is enabled, the DXMTFCS feature is over-ridden, and the 4 byte FCS will be added to the transmitted frame unconditionally. If APAD_XMT is clear, no pad field insertion will take place and runt packet transmission is possible. The disable FCS generation/transmission feature can be programmed dynamically on a frame by frame basis. See the ADD_FCS description of TMD1. Transmit FIFO Watermark (XMTFW in CSR80) sets the point at which the BMU requests more data from the transmit buffers for the FIFO. A minimum of "XMTFW" empty spaces must be available in the transmit FIFO before the BMU will request the system bus in order to transfer transmit packet data into the transmit FIFO. Transmit Start Point (XMTSP in CSR80) sets the point when the transmitter actually attempts to transmit a frame onto the media. A minimum of "XMTSP" bytes must be written to the transmit FIFO for the current frame before transmission of the current frame will begin. (When automatically padded packets are being sent, it is conceivable that the XMTSP is not reached when all of the data has been transferred to the FIFO. In this case, the transmission will begin when all of the packet data has been placed into the transmit FIFO.) When the entire frame is in the FIFO, attempts at transmission of preamble will commence regardless of the
Transmit Operation
The transmit operation and features of the PCnet-32 controller are controlled by programmable options. Transmit Function Programming Automatic transmit features such as retry on collision, FCS generation/transmission, and pad field insertion can all be programmed to provide flexibility in the (re-) transmission of messages. Disable retry on collision (DRTY) is controlled by the DRTY bit of the Mode register (CSR15) in the initialization block. Automatic pad field insertion is controlled by the APAD_XMT bit in CSR4. If APAD_XMT is set, auto-
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value in XMTSP. The default value of XMTSP is 10b, meaning 64 bytes full. Automatic Pad Generation Transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). This allows the minimum frame size of 64 bytes (512 bits) for 802.3/Ethernet to be guaranteed with no software intervention from the host/controlling process. Setting the APAD_XMT bit in CSR4 enables the automatic padding feature. The pad is placed between the LLC data field and FCS field in the 802.3 frame (see Figure 35). FCS is always added if the frame is padded, regardless of the state of DXMTFCS. The transmit frame will be padded by bytes with the value of 00h. The default value of APAD_XMT is 0; this will disable auto pad generation after H_RESET.
It is the responsibility of upper layer software to correctly define the actual length field contained in the message to correspond to the total number of LLC Data bytes encapsulated in the packet (length field as defined in the ISO 8802-3 (IEEE/ANSI 802.3) standard). The length value contained in the message is not used by the PCnet-32 controller to compute the actual number of pad bytes to be inser ted. The PCnet-32 controller will append pad bytes dependent on the actual number of bits transmitted onto the network. Once the last data byte of the frame has completed, prior to appending the FCS, the PCnet-32 controller will check to ensure that 544 bits have been transmitted. If not, pad bytes are added to extend the frame size to this value, and the FCS is then added.
Preamble 1010....1010 56 Bits
Sync 10101011 8 Bits
Destination Address 6 Bytes
Source Address 6 Bytes
Length
LLC Data
Pad
FCS
2 Bytes 46 -- 1500 Bytes
4 Bytes
Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
The 544 bit count is derived from the following: Minimum frame size (excluding preamble, including FCS) Preamble/SFD size FCS size 64 bytes 512 bits
Transmit FCS Generation Automatic generation and transmission of FCS for a transmit frame depends on the value of DXMTFCS bit in CSR15. When DXMTFCS = 0 the transmitter will generate and append the FCS to the transmitted frame. I f t h e a u t o m a t i c p a d d i n g fe a t u r e i s i n vo k e d (APAD_XMT is set in CSR4), the FCS will be appended by the PCnet-32 controller regardless of the state of DXMTFCS. Note that the calculated FCS is transmitted most significant bit first. The default value of DXMTFCS is 0 after H_RESET. Transmit Exception Conditions Exception conditions for frame transmission fall into two distinct categories. Those which are the result of normal network operation, and those which occur due to abnormal network and/or host related events. Normal events which may occur and which are handled autonomously by the PCnet-32 controller include collisions within the slot time with automatic retry. The PCnet-32 controller will ensure that collisions which occur within 512 bit times from the start of transmission (including preamble) will be automatically retired with no host intervention. The transmit FIFO ensures this by
8 bytes 4 bytes
64 bits 32 bits
To be classed as a minimum size frame at the receiver the transmitted frame must contain: Preamble + (Min Frame Size + FCS) bits At the point that FCS is to be appended, the transmitted frame should contain: Preamble + (Min Frame Size-FCS) bits 64 + (512-32) bits A minimum length transmit frame from the PCnet-32 controller will, therefore, be 576 bits, after the FCS is appended. The Ethernet specification assumes that minimum length messages will be at least 64 bytes in length.
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guaranteeing that data contained within the FIFO will not be overwritten until at least 64 bytes (512 bits) of preamble plus address, length and data fields have been transmitted onto the networ k without encountering a collision. If 16 total attempts (initial attempt plus 15 retries) fail, the PCnet-32 controller sets the RTRY bit in the current transmit TDTE in host memory (TMD2), gives up ownership (resets the OWN bit to zero) for this frame, and processes the next frame in the transmit ring for transmission. Abnormal network conditions include: s Loss of carrier. s Late collision. s SQE Test Error (does not apply to 10BASE-T port) None of the abnormal network conditions should not occur on a correctly configured 802.3 network, and will be reported if they do. When an error occurs in the middle of a multi-buffer frame transmission, the error status will be written in the current desc r iptor. The OWN bit(s) in the subsequent descriptor(s) will be reset until the STP (the next frame) is found. Loss of Carrier A loss of carrier condition will be reported if the PCnet-32 controller cannot observe receive activity while it is transmitting on the AUI port. After the PCnet-32 controller initiates a transmission it will expect to see data "looped-back" on the DI pair. This will internally generate a "carrier sense," indicating that the integrity of the data path to and from the MAU is intact, and that the MAU is operating correctly. This "carrier sense" signal must be asserted about 6 bit times before the last transmitted bit on DO. If "carrier sense" does not become active in response to the data transmission, or becomes inactive before the end of transmission, the loss of carrier (LCAR) error bit will be set in TMD2 after the frame has been transmitted. The frame will not be retried on the basis of an LCAR error. When the 10BASE-T port is selected, LCAR will be reported for every frame transmitted during the Link fail condition. Late Collision A late collision will be reported if a collision condition occurs after one slot time (512 bit times) after the transmit process was initiated (first bit of preamble commenced). The PCnet-32 controller will abandon the transmit process for the particular frame, set Late Collision (LCOL) in the associated TMD2, and process the next transmit frame in the ring. Frames experiencing a late collision will not be retried. Recovery from this condition must be performed by upper layer software.
SQE Test Error During the inter packet gap time following the completion of a transmitted message, the AUI CI pair is asserted by some transceivers as a self-test. The integral Manchester Encoder/Decoder will expect the SQE Test Message (nominal 10 MHz sequence) to be returned via the CI pair, within a 40 network bit time period after DI goes inactive (this does not apply if the 10BASE-T port is selected). If the CI input is not asserted within the 40 network bit time period following the completion of transmission, then the PCnet-32 controller will set the CERR bit in CSR0. CERR will be asserted in 10BASE-T mode after transmit if T-MAU is in Link Fail state. CERR will never cause INTR to be activated. It will, however, set the ERR bit in CSR0.
Receive Operation
The receive operation and features of the PCnet-32 controller are controlled by programmable options. Receive Function Programming Automatic pad field stripping is enabled by setting the ASTRP_RCV bit in CSR4. this can provide flexibility in the reception of messages using the 802.3 frame format. All receive frames can be accepted by setting the PROM bit in CSR15. When PROM is set, the PCnet-32 controller will attempt to receive all messages, subject to minimum frame enforcement. Promiscuous mode overrides the effect of the Disable Receive Broadcast bit on receiving broadcast frames. The point at which the BMU will start to transfer data from the receive FIFO to buffer memory is controlled by the RCVFW bits in CSR80. The default established during H_RESET is 10b which sets the threshold flag at 64 bytes empty. Automatic Pad Stripping During reception of an 802.3 frame the pad field can be stripped automatically. ASTRP_RCV (CSR4, bit 10) = 1 enables the automatic pad stripping feature. The pad field will be stripped before the frame is passed to the FIFO, thus preserving FIFO space for additional frames. The FCS field will al so be s tr i ppe d, s in ce it i s co mpu ted at th e transmitting station based on the data and pad field characters, and will be invalid for a receive frame that has had the pad characters stripped. The number of bytes to be stripped is calculated from the embedded length field, as defined in the ISO 88023 (IEEE/ANSI 802.3) definition, contained in the frame. The length indicates the actual number of LLC data bytes contained in the message. Any received frame which contains a length field less than 46 bytes will have the pad field stripped (if ASTRP_RCV is set).
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Receive frames which have a length field of 46 bytes or greater will be passed to the host unmodified. Note that for some network protocols, the value passed in the Ethernet Type and/or 802.3 Length field is not compliant with either standard and may cause problems. Figure 36 shows the byte/bit ordering of the received length field for an 802.3 compatible frame format.
Receive FCS Checking Reception and checking of the received FCS is performed automatically by the PCnet-32 controller. Note that if the Automatic Pad Stripping feature is enabled, the FCS for padded frames will be verified against the value computed for the incoming bit stream including pad characters, but the FCS value for a padded frame will not be passed to the host. If an FCS error is detected in any frame, the error will be reported in the CRC bit in RMD1.
46 N 1500 Bytes 56 Bits Preamble 1010....1010 8 Bits Sync 10101011 6 Bytes Destination Address 6 Bytes Source Address 2 Bytes Length LLC Data 1 N 1500 Bytes Pad 4 Bytes FCS
45 N 0 Bytes
Start of Frame at Time = 0 Bit 0 Bit 7 Bit 0 Bit 7
Increasing Time Most Significant Byte Least Significant Byte
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Figure 36. ISO 8802.3 (IEEE/ANSI 802.3) Data Frame
Receive Exception Conditions Exception conditions for frame reception fall into two distinct categories: Those which are the result of normal network operation, and those which occur due to abnormal network and/or host related events. Normal events which may occur and which are handled autonomously by the PCnet-32 controller are basically collisions within the slot time and automatic runt packet rejection. The PCnet-32 controller will ensure that collisions which occur within 512 bit times from the start of reception (excluding preamble) will be automatically d e l e t e d f r o m t h e r e c e i ve F I F O w i t h n o h o s t intervention. The receive FIFO will delete any frame which is composed of fewer than 64 bytes provided that the Runt Packet Accept (RPA bit in CSR124) feature has not been enabled. This criterion will be met regardless of whether the receive frame was the first
(or only) frame in the FIFO or if the receive frame was queued behind a previously received message. Abnormal network conditions include: s FCS error s Late collision Host-related receive exception conditions include MISS, BUFF, and OFLO. These are described in the BMU section.
Loopback Operation
Loopback is a mode of operation intended for system testing. In this mode the transmitter and receiver are both operating at the same time so that the controller receives its own transmissions. The controller provides two types of internal loopback and one type of external loopback. In internal loopback mode the transmitter
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data can be looped back to the receiver at one of two places inside the controller without actually transmitting any data to the external network. The receiver will move the received data to the external network. The receiver will move the received data to the next receive buffer, where it can be examined by software. Alternatively, in external loopback mode, data can be transmitted to and received from the external network. There are restrictions on loopback operation. The PCnet-32 controller has only one FCS generator circuit. The FCS generator can be used by the transmitter to generate the FCS that is appended to the frame, or it can be used by the receiver to verify the FCS of the received frame. It can not be used by the receiver and transmitter at the same time. If the FCS generator is connected to the receiver, the transmitter will not append an FCS to the frame, but the receiver will check for one. The user can, however, calculate the FCS value for a frame and include this four-byte number in the transmit buffer. If the FCS generator is connected to the transmitter, the transmitter will append an FCS to the frame, but the receiver will not check it. However, the user can verify the FCS by software. During loopback the FCS logic can be allocated to the receiver by setting DXMTFCS = 1 in CSR15. If DXMTFCS=0, the MAC Engine will calculate and append the FCS to the transmitted message. The receive message passed to the host will therefore contain an a d d i t i o n a l 4 b y t e s o f F C S. I n t h i s l o o p b a ck configuration, the receive circuitry cannot detect FCS errors if they occur. If DXMTFCS=1, the last four bytes of the transmit message must contain the (software generated) FCS computed for the transmit data preceding it. The MAC Engine will transmit the data without addition of an FCS field, and the FCS will be calculated and verified at the receiver. The loopback facilities of the MAC Engine allow full operation to be verified without disturbance to the network. Loopback operation is also affected by the state of the Loopback Control bits (LOOP, MENDECL, and INTL) in CSR15. This affects whether the internal MENDEC is considered part of the internal or external loop-back path. The multicase address detection logic uses the FCS generator. Therefore, when in the loopback mode(s), the multicast address detection feature of the MAC Engine, programmed by the contents of the Logical Address Filter (LADRF [63:0] in CSRs 8-11) can only be tested when DXMTFCS=1, allocating the FCS generator to the receiver. All other features operate identically in loopback as in normal operation, such as automatic transmit padding and receive pad stripping.
When performing an internal loopback, no frame will be transmitted to the network. However, when the PCnet-32 controller is configured for internal loopback the receiver will not be able to detect network traffic. External loopback tests will transmit frames onto the network when the AUI port is selected. Runt Packet Accept is automatically enabled when any loopback mode is invoked. Loopback mode can be performed with any frame size. Runt Packet Accept is internally enabled (RPA bit in CSR 124 is not affected) when any loopback mode is invoked. This is to be backwards compatible to the LANCE (Am7990) software. When external loopback is perfor med while the 10BASE-T MAU is selected, collision detection is disabled. This is necessary, because a collision in a 10BASE-T system is defined as activity on the transmitter outputs and receiver inputs at the same time, which is exactly what happens during external loopback. Since a 10BASE-T hub does not normally feed the station's transmitter outputs back into the station's receiver inputs, the use of external loopback in a 10BASE-T system usually requires some sort of external hardware that connects the outputs of the 10BASE-T MAU to its inputs.
LED Support
The PCnet-32 controller can support up to 4 LEDs. LED outputs LNKST, LED1 and LED2 allow for direct connection of an LED and its supporting pull-up device. LED output LEDPRE3 may require an additional buffer between the PCnet-32 controller output pin and the LED and its supporting pull-up device. Because the LEDPRE3 output is multiplexed with other PCnet-32 controller functions, it may not always be possible to connect an LED circuit directly to the LEDPRE3 pin. For example, when an LED circuit is directly connected to the EEDO/LEDPRE3/SRD pin, then it is not possible for most serial EEPROM devices to sink enough IOL to maintain a valid low level on the EEDO input to the PCnet-32 controller. Therefore, in applications that require both an EEPROM and a fourth LED, then it is necessary to buffer the LEDPRE3 circuit from the EEPROM-PCnet-32 controller connection. The LED registers in the BCR resource space allow each LED output to be programmed for either active high or active low operation, so that both inverting and non-inverting buffering choices are possible. In applications where an EEPROM is not needed, the LEDPRE3 pin may be directly connected to an LED circuit. The PCnet-32 controller LEDPRE3 pin driver will be able to sink enough current to properly drive the LED circuit.
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By default, after H_RESET, the 4 LED outputs are configured as shown in Table 40.
Table 40. LED Configuration
LED Output LNKST LED1 LED2 LEDPRE3 Default Interpretation Link Status Receive Default Drive Enable Enabled Enabled Default Output Polarity Active LOW Active LOW Active LOW Active LOW
Receive Polarity Enabled Transmit Enabled
For each LED register, each of the status signals is ANDed with its enable signal, and these signals are all OR'd together to form a combined status signal. Each LED pin's combined status signal runs to a pulse stretcher, which consists of a 3-bit shift register clocked at 38 Hz (26 ms). The data input of each shift register is normally at logic 0. The OR gate output for each LED register asynchronously sets all three bits of its shift register when the output becomes asserted. The inverted output of each shift register is used to control an LED pin. Thus the pulse stretcher provides 2-3 clocks of stretched LED output, or 52 ms to 78 ms. Figure 37 shows the LED signal circuit that exists for each LED pin.
LNKST LNKST E RCVM RCVM E XMT XMT E RXPOL RXPOL E RCV RCV E JAB JAB E COL COL E To Pulse Stretcher
Figure 37. On-Chip LED Control Logic
H_RESET, S_RESET and STOP
There are three different types of RESET operations that may be performed on the PCnet-32 device, H_RESET, S_RESET and STOP. These names have been used throughout the document. The following is a description of each type of RESET operation: H_RESET H_RESET= HARDWARE_RESET is a PCnet-32 RESET operation that has been created by the proper assertion of the RESET pin of the PCnet-32 device. When the minimum pulse width timing as specified in the RESET pin description has been satisfied, then an internal RESET operation will be performed. H_RESET will RESET all of or some portions of CSR0, 3, 4, 15, 58, 80, 82, 100, 112, 114, 122, 124 and 126 to default values; H_RESET will RESET all of or some portions of BCR 2, 4, 5, 6, 7, 18, 19, 20, 21 to default values. H_RESET will cause the microcode program to jump to its RESET state. Following the end of the
H_RESET operation, the PCnet-32 controller will attempt to read the EEPROM device through the EE PROM mic r owir e in ter fac e. The H_ RES ET operation will unconditionally cause all INTR pins to become inactive. (Note that there may be either 2 or 4 INTR pins, depending upon the JTAGSEL pin setting.) The H_RESET operation will unconditionally cause the HOLD signal to become de-asserted. H_RESET will reset T-MAU to Link Fail state. H_RESET is generated by proper assertion of either the RESET or RESET pin, depending upon the mode that has been selected through the LB/VESA pin. S_RESET S_RESET = SOFTWARE_RESET is a PCnet-32 RESET operation that has been created by a read access to the RESET REGISTER which is located at offset 14h from the PCnet-32 controller I/O base address.
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S_RESET will RESET all of or some portions of CSR0, 3, 4, 15, 80, 100 and 124 to default values. S_RESET will RESET NONE of the BCR locations to default values. S_RESET will cause the microcode program to jump to its RESET state. Following the end of the S_RESET operation, the PCnet-32 controller will NOT attempt to read the EEPROM device. See also the subsection on RESET Register in the I/O Register Access section under Software Access. The S_RESET operation will not cause INTR pins to become inactive. S_RESET will set the T-MAU into Link Fail state. Note that S_RESET will not cause a de-assertion of the HOLD signal, if it happens to be active at the time of the read to the reset register. The HOLD signal will remain active until the HLDA signal is synchronously sampled as asserted. Following the read of the RESET register, on the next clock cycle after the HLDA signal is synchronously sampled as asserted, (except in Am386 mode, when two cycles are needed) the PCnet32 controller will de-assert the HOLD signal; No bus
master accesses will have been performed during this brief bus ownership period. STOP STOP is a PCnet-32 RESET operation that has been created by the ASSERTION of the STOP bit in CSR0. That is, a STOP RESET is generated by writing a ONE to the STOP bit of CSR0 when the STOP bit currently has a value of ZERO. If the STOP bit value is currently a ONE, and a ONE is rewritten to the STOP bit, then NO STOP RESET will be generated. The STOP operation will not cause INTR pins to become inactive. STOP will RESET all or some portions of CSR0, 3, and 4 to default values; STOP will RESET NONE of the BCR locations to default values. STOP will cause the microcode program to jump to its RESET state. Following the end of the STOP operation, the PCnet-32 controller will not attempt to read the EEPROM device. For the identity of individual CSRs and bit locations that are affected by STOP, see the individual CSR register descriptions. Setting the STOP bit does not affect the T-MAU.
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USER ACCESSIBLE REGISTERS
The PCnet-32 controller implements all PCnet-ISA (Am79C960) registers, all LANCE (Am7990) registers, all ILACC (Am79C900) registers, plus a number of additional registers. The PCnet-32 controller registers are compatible with both the PCnet-ISA (Am79C960) registers and all of the LANCE (Am7990) registers upon power up. Compatibility to the ILACC set of registers requires one access to the Software Style register (BCR20, bits 7-0) to be performed. By setting an appropriate value of the Software Style register (BCR20, bits 7-0) the user can select a set of registers that are compatible with the ILACC set of registers. Note that all register locations are defined to be 16 bits in width when WIO mode is selected. When DWIO mode is selected, all register locations are defined to be 32 bits in width. When performing register write operations in DWIO mode, the upper 16 bits should always be written as zeros, except APROM locations. When performing register read operations in DWIO mode, the upper 16 bits of I/O resources should always be written as ZEROs, except for APROM locations and CSR88. When performing register read operations in DWIO mode, the upper 16 bits of I/O resources should always be regarded as having undefined values, except for the APROM locations and CSR88. PCnet-32 controller registers can be divided into three groups: Setup registers: Registers that are intended to be initialized by the system initialization procedure (e.g. BIOS device initialization routine) or by the device driver to program the operation of various PCnet-32 controller features Running registers: Registers that are intended to be used by the device driver software once the PCnet-32 controller is running to access status information and to pass control information Test registers: Registers that are intended to be used only for testing and diagnostic purposes Below is a list of the registers that fall into each of the first two categories. Those registers that are not included in either of these lists can be assumed to be intended for diagnostic purposes. Setup Registers The following is a list of those registers that would typically need to be programmed once during the setup of the PCnet-32 controller within a system. The control bits in each of these registers typically do not need to be modified once they have been written. However, there are no restrictions as to how many times these registers may actually be accessed. Note that if the default power up values of any of these registers is acceptable to the application, then such registers need
never be accessed at all. Also note that some of these registers may be programmable through the EEPROM read operation, and therefore do not necessarily need to be written to by the system initialization procedure or by the driver software. CRS1 CSR2 CSR3 CSR4 CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR24 CSR25 CSR30 CRS31 CSR47 CSR58 CSR76 CSR78 CSR80 CSR82 CSR100 CSR122 BCR2 BCR16 BCR17 BCR18 BCR19 BCR20 BCR21 Initialization Address[15:0] Initialization Address[31:16] Interrupt Masks and Deferral Control Test and Features Control Logical Address Filter [15:0] Logical Address Filter [31:16] Logical Address Filter [47:32] Logical Address Filter [63:48] Physical Address Filter [15:0] Physical Address Filter [31:16] Physical Address Filter [47:32] Mode Register Base Address of Receive Ring Lower Base Address of Receive Ring Upper Base Address of Transmit Ring Lower Base Address of Transmit Ring Upper Polling Interval Software Style Receive Ring Length Transmit Ring Length Cycle Register and FIFO Threshold Control Bus Activity Timer Memory Error Time-out Register Receiver Packet Alignment Control MAU configuration I/O Base Address Lower I/O Base Address Upper Bus Size and Burst Control Register EEPROM Control and Status Register Software Style Interrupt Control
Running Registers The following is a list of those registers that would typically need to be periodically read and perhaps written during the normal running operation of the PCnet-32
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controller within a system. Each of these registers contains control bits or status bits or both. RAP CSR0 CSR4 CSR112 CSR114 Register Address Port Register PCnet-32 Controller Status Register Test and Features Control Missed Frame Count Receive Collision Count
serves as the pointer to BCR space, which is described in a later section. CSR0: PCnet-32 Controller Status Bit 31-16 15 Name RES ERR Description Reserved locations. Written zeros and read as undefined. as
Error is set by the ORing of BABL, CERR, MISS, and MERR. ERR remains set as long as any of the error flags are true. ERR is read only. Write operations are ignored.
RAP Register
The RAP (Register Address Pointer) register is used to gain access to CSR and BCR registers on board the PCnet-32 controller. The value of the RAP indicates the address of a CSR or BCR whenever an RDP or BDP access is performed. That is to say, RAP serves as a pointer to CSR and BDP space. As an example of RAP use, consider a read access to CSR4. In order to access this register, it is necessary to first load the value 0004 into the RAP by performing a write access to the RAP offset of 12h (12h when WIO mode has been selected, 14h when DWIO mode has been selected). The data for the RAP write would be 0004. Then a second access is performed on the PCnet-32 controller, this time to the RDP offset of 10h (for either WIO or DWIO mode). The RDP access is a read access, and since RAP has just been loaded with the value of 0004, the RDP read will yield the contents of CSR4. A read of the BDP at this time (offset of 16h when WIO mode has been selected, 1Ch when DWIO mode has been selected) will yield the contents of BCR4, since the RAP is used as the pointer into both BDP and RDP space.
14
BABL
Babble is a transmitter time-out error. It indicates that the transmitter has been on the channel longer than the time required to send the maximum length frame. BABL will be set if 1519 bytes or greater are transmitted. When BABL is set, INTR is asserted if IENA = 1 and the mask bit BABLM in CSR3 is clear. BABL assertion will set the ERR bit. BABL is set by the MAC layer and cleared by writing a "1". Writing a "0" has no effect. BABL is cleared by H_RESET or S_RESET or setting the STOP bit.
13
CERR
RAP: Register Address Port Bit 31-16 15-8 7-0 Name RES RES RAP Description Reserved locations. Written zeros and read as undefined. Reserved locations. written as zeros. Read as and
Collision Error indicates that the collision inputs to the AUI port failed to activate within 20 network bit times after chip terminated transmission (SQE Test). This feature is a transceiver test feature. In 10BASE-T mode CERR will be set if a transmission is attempted while the T-MAU is in Link Fail state. CERR assertion will not result in an interrupt being generated. CERR assertion will set the ERR bit. CERR is set by the MAC layer and cleared by writing a "1". Writing a "0" has no effect. CERR is cleared by H_RESET or S_RESET or setting the STOP bit.
Register Address Port. The value of these 8 bits determines which CSR or BCR will be accessed when an I/ O access to the RDP or BDP port, respectively, is performed. RAP is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 12 MISS
Control and Status Registers The CSR space is accessible by performing accesses to the RDP (Register Data Port). The particular CSR that is read or written during an RDP access will depend upon the current setting of the RAP. RAP serves as a pointer into the CSR space. RAP also
Missed Frame is set when PCnet-32 controller has lost an incoming receive frame resulting from a R e c e i ve D e s c r i p t o r n o t b e i n g ava i l a bl e. T h i s bi t i s t h e o n l y immediate indication that receive data has been lost since there is no
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current receive descriptor to write status to. When MISS is set, INTR is asserted if IENA = 1 and the mask bit MISSM in CSR3 is clear. MISS assertion will set the ERR bit. MISS is set by the Buffer Management Unit and cleared by writing a "1". Writing a "0" has no effect. MISS is cleared by H_RESET or S_RESET or setting the STOP bit. 11 MERR Memory Error is set when PCnet-32 controller requests the use of the system interface bus by asserting HOLD and has not received HLDA asser tion after a programmable length of time.The length of time in microseconds before MERR is asser ted will depend upon the setting of the Bus Time-Out Register (CSR100). The default setting of CSR100 will give a MERR after 51.2 s of bus latency. When MERR is set, INTR is asserted if IENA = 1 and the mask bit MERRM in CSR3 is clear. MERR asser tion will set the ERR bit, regardless of the settings of IENA and MERRM. MERR is set by the Bus Interface Unit and cleared by writing a "1". Writing a "0" has no effect. MERR is cleared by H_RESET or S_RESET or by setting the STOP bit. 10 RINT Receive interrupt. RINT is set by the Buffer Management Unit of the PCnet-32 controller after the last descriptor of a receive packet has been updated by writing a ZERO to the ownership bit. RINT may also be set when the first descriptor of a receive packet has been updated by writing a ZERO to the ownership bit if the SPRINTEN bit of CSR3 has been set to a ONE. When RINT is set, INTR is asserted if IENA = 1 and the mask bit RINTM in CSR3 is clear. RINT is cleared by the host by writing a "1". Writing a "0" has no effect. RINT is cleared by H_RESET or S_RESET or by setting the STOP bit.
9
TINT
Transmit interrupt is set after completion of a transmit frame and toggling of the OWN bit in the last buffer in the Transmit Descriptor Ring. When TINT is set, INTR is asserted if IENA = 1 and the mask bit TINTM in CSR3 is clear. TINT is set by the Buffer Management Unit after the last transmit bu f fe r h a s b e e n u p d a t e d a n d cleared by writing a "1". Writing a "0" has no effect. TINT is cleared by H_RESET or S_RESET or setting the STOP bit.
8
IDON
Initialization Done indicates that the initialization sequence has completed. When IDON is set, PCnet-32 controller has read the Initialization block from memory. When IDON is set, INTR is asserted if IENA = 1 and the mask bit IDONM in CSR3 is clear. IDON is set by the Buffer Management Unit after the initialization block has been read from memory and cleared by writing a "1". Writing a "0" has no effect. IDON is cleared by H_RESET or S_RESET or setting the STOP bit.
7
INTR
Interrupt Flag indicates that one or more following interrupt causing conditions has occurred: BABL, MISS, MERR, MFCO, RCVCCO, RINT, RPCO, TINT, IDON, JAB or TXSTRT. and its associated mask bit is clear. If IENA = 1 and INTR is set, INTR will be active. INTR is read only. INTR is cleared by H_RESET or S_RESET or by setting the STOP bit or by clearing all of the active individual interrupt bits that have not been masked out.
6
IENA
Interrupt Enable allows INTR to be active if the interrupt Flag is set. If IENA = "0" then INTR will be disabled regardless of the state of INTR. IENA is set by writing a "1" and cleared by writing a "0". IENA is cleared by H_RESET or S_RESET or setting the STOP bit.
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5
RXON
Receive On indicates that the Receive function is enabled. RXON is set if DRX (CSR15[0]) = "0" after the START bit is set. If INIT and START are set together, RXON will not be set until after the initialization block has been read in. RXON is read only. RXON is cleared by H _ R E S E T o r S _ R E S E T o r setting the STOP bit.
management operations. Setting STRT clears the STOP bit. If STRT and INIT are set together, PCnet-32 c ontr ol ler in iti al iz atio n wi ll b e performed first. STRT is set by writing a "1". Writing a "0" has no effect. STRT is cleared by H_RESET or S_RESET or by setting the STOP bit. 0 INIT INIT assertion enables PCnet-32 controller to begin the initialization p r o c e d u r e w h i c h r ea d s i n t h e initialization block from memory. Setting INIT clears the STOP bit. If STRT and INIT are set together, PCnet-32 controller initialization will be performed first. INIT is not cleared when the initialization sequence has completed. INIT is set by writing a "1". Writing a "0" has n o e f fe c t . I N I T i s c l e a r e d b y H _ R E S E T o r S _ R E S E T o r by setting the STOP bit. CSR1: IADR[15:0] Bit 31-16 15-0 Name RES Description Reserved locations. Written zeros and read as undefined. as
4
TXON
Transmit On indicates that the Transmit function is enabled. TXON is set if DTX (CSR15[1]) = "0" after the START bit is set. If INIT and START are set together, TXON will not be set until after the initialization block has been read in. TXON is read only. TXON is cleared by H_RESET or S_RESET or setting the STOP bit. Transmit Demand, when set, causes the Buffer Management Unit to access the Transmit Descriptor Ring without waiting for the poll-time counter to elapse. If TXON is not enabled, TDMD bit will be reset and no Transmit Descriptor Ring access will occur. TDMD is required to be set if the DPOLL bit in CSR4 is set. Setting TDMD while DPOLL = 0 merely hastens the PCnet-32 controller's response to a Transmit Descriptor Ring Entry. TDMD is set by writing a "1". Writing a "0" has no effect. TDMD will be cleared by the Buffer Management Unit when it fetches a Transmit Descriptor. TDMD is cleared by H_RESET or S_RESET or setting the STOP bit.
3
TDMD
IADR[15:0] Lower 16 bits of the address of the Initialization Block. Regardless of the value of SSIZE32(BCR20/CSR58, bit 8) IADR[1:0] must be zero. This register is aliased with CSR16. Read/Write accessible only when t h e S TO P b i t i n C S R 0 i s s e t . Unaffected by H_RESET or S_RESET or by setting the STOP bit.
2
STOP
STOP assertion disables the chip from all DMA activity. The chip remains inactive until either STRT or INIT are set. If STOP, STRT and INIT are all set together, STOP will override STRT and INIT. STOP is set by writing a "1" or by H_RESET or S_RESET. Writing a "0" has no effect. STOP is cleared by setting either STRT or INIT.
CSR2: IADR[31:16] Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
15-8 IADR[31:24] If SSIZE32 is set (BCR20[8]), then the IADR[31:24] bits will be used strictly as the upper 8 bits of the initialization block address. However, if SSIZE32 is reset, then the IADR[31:24] bits will be used to generate the upper 8 bits of all bus
1
STRT
STRT assertion enables PCnet-32 controller to send and receive f r a m e s , a n d p e r fo r m b u f fe r
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mastering addresses, as required for a 32 bit address bus. Note that the 1 6- bi t so ftwar e s tr uc tur es specified by the SSIZE32 = 0 setting will yield only 24 bits of address for PCnet-32 controller bus master accesses, while the 32-bit hardwa r e fo r w h i c h t h e P C n e t - 3 2 controller is intended will require 32 b i t s o f a d d r e s s . T h e r e fo r e , w h e n ev e r S S I Z E 3 2 = 0 , t h e IADR[31:24] bits will be appended to the 24-bit initialization address, to each 24-bit descriptor base address and to each beginning 24-bit buffer address in order to form complete 32-bit addresses. The upper 8 bits that exist in the descriptor address registers and the buffer address registers which are stored on board the PCnet-32 controller will be overwritten with the IADR[31:24] value, so that CSR accesses to these registers will show the 32 bit address that includes the appended field. If SSIZE32 = 1, then software will provide 32-bit pointer values for all of the shared software structures (i.e. descriptor bases and buffer a d d r e s s e s ) , a n d t h e r e fo r e , IADR[31:24] will not be written to the upper 8 bits of any of these resources, but it will be used as the upper 8 bits of the initialization address. Read/Write accessible only when t h e S TO P b i t i n C S R 0 i s s e t . U n a f fe c t e d b y H _ R E S E T o r S_RESET or by setting the STOP bit. 7-0 IADR[23:16] Bits 23 through 16 of the address of the Initialization Block. Whenever this register is written, CSR17 is updated with CSR2's contents. Read/Write accessible only when t h e S TO P b i t i n C S R 0 i s s e t . U n a f fe c t e d b y H _ R E S E T o r S_RESET or by setting the STOP bit.
CSR3: Interrupt Masks and Deferral Control Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15 14 RES BABLM
Reserved location. Read and written as zero. Babble Mask. If BABLM is set, the BABL bit in CSR0 will be masked and unable to set INTR flag in CSR0. Read/Write accessible always. BABLM is cleared by H_RESET or S_RESET and is not affected by STOP.
13 12
RES MISSM
Reserved location. Read and written as zero. Missed Frame Mask. If MISSM is set, the MISS bit in CSR0 will be masked and unable to set INTR flag in CSR0. Read/Write accessible always. MISSM is cleared by H_RESET or S_RESET and is not affected by STOP.
11
MERRM
Memory Error Mask. If MERRM is set, the MERR bit in CSR0 will be masked and unable to set INTR flag in CSR0. Read/Write accessible always. MERRM is cleared by H_RESET or S_RESET and is not affected by STOP.
10
RINTM
Receive Interrupt Mask. If RINTM is set, the RINT bit in CSR0 will be masked and unable to set INTR flag in CSR0. Read/Write accessible always. RINTM is cleared by H_RESET or S_RESET and is not affected by STOP.
9
TINTM
Transmit interrupt Mask. If TINTM is set, the TINT bit in CSR0 will be masked and unable to set INTR flag in CSR0. Read/Write accessible always. TINTM is cleared by H_RESET or S_RESET and is not affected by STOP.
8
IDONM
Initialization Done Mask. If IDONM is set, the IDON bit in CSR0 will be
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masked and unable to set INTR flag in CSR0. Read/Write accessible always. IDONM is cleared by H_RESET or S_RESET and is not affected by STOP. 7 6 RES Reserved location. Read and written as zeroes.
controller will begin writing the next frame's data to the buffer pointed to by that descriptor. Note that because several descriptors may be allocated by the host for each frame, and not all messages may need all of the de sc r i pt or s tha t ar e al lo c ate d between descriptors that contain STP = ONE, then some descriptors/ buffers may be skipped in the ring. While performing the search for the next STP bit that is set to ONE, the PCnet-32 controller will advance through the receive descriptor ring regardless of the state of ownership bits. If any of the entries that are ex a m i n e d d u r i n g t h i s s e a r c h indicate PCnet-32 controller ownership of the descriptor but also indicate STP = "0", then the PCnet-32 controller will RESET the OWN bit to ZERO in these entries. If a scanned entr y indicates host ownership with STP = "0" then the PCnet-32 controller will not alter the entry, but will advance to the next entry. When the STP bit is found to be true, but the descriptor that contains this setting is not owned by the P C n e t - 3 2 c o n t r o l l e r, t h e n t h e PCnet-32 controller will stop advancing through the ring entries and begin periodic polling of this entry. When the STP bit is found to be true, and the descriptor that contains this setting is owned by the P C n e t - 3 2 c o n t r o l l e r, t h e n t h e PCnet-32 controller will stop advancing through the ring entries, store the descriptor information that it has just read, and wait for the next receive to arrive. This behavior allows the host software to preassign buffer space in such a manner that the "header" portion of a receive frame will always be written to a particular memory area, and the "data" portion of a receive frame will always be written to a separate memory area. The interrupt is generated when the "header" bytes have been written to the "header" memory area.
DXSUFLO Disable Transmit Stop on Underflow error. When DXSUFLO (CSR3, bit 6) is set to ZERO, the transmitter is turned off when an UFLO error occurs (CSR0, TXON = 0). When DXSUFLO is set to ONE, the PCnet-32 controller gracefully recovers from an UFLO error. It scans the transmit descriptor ring until it finds the start of a new frame and starts a new transmission. Read/Write accessible always. DXSUFLO is cleared by H_RESET or S_RESET and is not affected by STOP.
5
LAPPEN Look-Ahead Packet Processing Enable. When set to a ONE, the LAPPEN bit will cause the PCnet-32 controller to generate an interrupt fo l l ow i n g t h e d e s c r i p t o r w r i t e operation to the first buffer of a receive frame. This interrupt will be generated in addition to the interrupt that is generated following the descriptor write operation to the last buffer of a receive frame. The interrupt will be signaled through the RINT bit of CSR0. Setting LAPPEN to a ONE also enables the PCnet-32 controller to read the STP bit of receive descriptors. The PCnet-32 controller will use the STP information to determine where it should begin writing a receive frame's data. Note that while in this mode, the P Cn et- 3 2 c on tr o ll e r c an wr i t e intermediate frame data to buffers whose descriptors do not contain STP bits set to ONE. Following the write to the last descriptor used by a frame, the PCnet-32 controller will scan through the next descriptor entries to locate the next STP bit that is set to a ONE. The PCnet-32
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Read/Write accessible always. The LAPPEN bit will be reset to ZERO by H_RESET or S_RESET and will be unaffected by STOP. See Appendix D for more information on the LAPP concept. 4 DXMT2PD Disable Transmit Two Part Deferral. If DXMT2PD is set, Transmit Two Part Deferral will be disabled. Read/Write accessible always. DXMT2PD is cleared by H_RESET or S_RESET and is not affected by STOP. 3 EMBA Enable Modified Back-off Algorithm. If EMBA is set, a modified back-off algorithm is implemented. Read/Write accessible always. EMBA is cleared by H_RESET or S_RESET and is not affected by STOP. 2 BSWP Byte Swap. This bit is used to c hoo se be twe en bi g an d l it tl e Endian modes of operation. When BSWP is set to a ONE, big Endian mode is selected. When BSWP is set to ZERO, little Endian mode is selected. When big Endian mode is selected, the PCnet-32 controller will swap the order of bytes on the data bus during FIFO transfers only. Specifically, D31-24 becomes Byte0, D23-16 becomes Byte1, D15-8 becomes Byte2 and D7-0 becomes Byte3 when big Endian mode is selected. When little Endian mode is selected, the order of bytes on the data bus is: D31-24 is Byte3, D23-16 is Byte2, D15-8 is Byte1 and D7-0 is Byte0. Byte swap only affects data transfers that involve the FIFOs. Initialization block transfers are not affected by the setting of the BSWP bit. Descriptor transfers are not affected by the setting of the BSWP bit. RDP, RAP and BDP accesses are not affected by the setting of the BSWP bit. APROM transfers are not affected by the setting of the BSWP bit. BSWP is write/readable regardless of the state of the STOP bit. BSWP is cleared by H_RESET or
S_RESET and is not affected by STOP. 1-0 RES Reserved locations. The default value is ZERO for both locations. Writing a ONE to these bits has no effect on device function; if a ONE is written to these bits, then a ONE will be read back. Existing drivers may w r i t e a O N E t o t h e s e b i t s fo r compatibility, but new drivers should write a ZERO to these bits and should treat the read value as undefined. Description Reserved locations. Written zeros and read as undefined. as
CSR4: Test and Features Control Bit Name 31-16 RES 15 ENTST
Enable Test Mode operation. Setting ENTST to ONE enables internal test functions which are useful only for s ta n d al o n e in t egra t ed c i r c u i t testing. In addition, the Runt Packet Accept (RPA) bit (CSR124, bit 3) may be changed only when ENTST is set to ONE. To enable RPA, the user must first write a ONE to the ENTST bit. Next, the user must first write a ONE to the RPA bit (CSR124, bit 3). Finally, the user must write a ZERO to the ENTST bit to take the device out of test mode operation. Once the RPA bit has been set to ONE, the device will remain in the Runt Packet Accept mode until the RPA bit is cleared to ZERO. Read/Write accessible. ENTST is cleared by H_RESET or S_RESET and is unaffected by the STOP bit.
14 DMAPLUS
When DMAPLUS = "1", disables the burst transaction counter, CSR80. If DMAPLUS = "0", the burst transaction counter is enabled. Read and Write accessible. DMAPLUS is cleared by H_RESET or S_RESET and is unaffected by the STOP bit.
13
TIMER
Timer Enable Register. If TIMER is set, the Bus Activity Timer Register, CSR82 is enabled. If TIMER is cleared, the Bus Activity Timer Register is disabled.
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Read/Write accessible. TIMER is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 12 DPOLL Disable Transmit Polling. If DPOLL is set, the Buffer Management Unit will disable transmit polling. Likewise, if DPOLL is cleared, automatic t ransmit polling is enabled. If DPOLL is set, TDMD bit in CSR0 must be periodically set in order to initiate a manual poll of a t r a n s m i t d e s c r i p t o r. Tr a n s m i t descriptor polling will not take place if TXON is reset. Read/Write accessible. DPOLL is cleared by H_RESET or S_RESET and is unaffected by the STOP bit. 11 APAD_XMT Auto Pad Transmit. When set, APAD_XMT enables the automatic padding feature. Transmit frames will be padded to extend them to 64 bytes including FCS. The FCS is calculated for the entire frame including pad, and appended after th e p ad f ie l d. APA D_ X MT wi ll override the programming of the DXMTFCS bit. Read and Write accessible. APAD_XMT is reset by H_RESET or S_RESET and is unaffected by the STOP bit. 10 ASTRP_RCV Auto Strip Receive. When set, ASTRP_RCV enables the automatic pad stripping feature. The pad and FCS fields will be stripped from receive frames and not placed in the FIFO. Read and Write accessible. ASTRP_RCV is reset by H_RESET or S_RESET and is unaffected by the STOP bit. 9 MFCO Missed Frame Counter Overflow interrupt. Indicates the MPC (CSR112) wrapped around. Can be cleared by writing a 1 to this bit. Also cleared by H_RESET or S_RESET or setting the STOP bit. Writing a 0 has no effect. When MFCO is set, INTR is asserted if IENA = 1 and the mask bit MFCOM is cleared. When the SWSTYLE register (BCR20[7:0]) has been pro7 6 RES RES
grammed to the ILACC compatibility mode, then this bit has no meaning and the PCnet-32 controller will never set the value of this bit to ONE. 8 MFCOM Missed Frame Counter Overflow Mask. If MFCOM is set, MFCO will be unable to set INTR in CSR0. Set to a ONE by H_RESET or S_RESET, unaffected by the STOP bit. When the SWSTYLE register (BCR20[7:0]) has been programmed to the ILACC compatibility mode, then this bit has no meaning and the PCnet-32 controller will set the value of this bit to a ZERO. Reserved location. Written as zero and read as zero. Reserved location. This bit may be written to as either a ONE or a ZERO, but will always be read as a ZERO. This bit has no effect on PCnet-32 controller operation.
5
RCVCCO Receive Collision Counter Overflow. Indicates the Receive Collision Counter (CSR114) wrapped around. Can be cleared by writing a 1 to this bit. Also cleared by H_RESET or S_RESET or by setting the STOP bit. Writing a 0 has no effect. When RCVCCO is set, INTR is asserted if IENA=1 and the mask bit RCVCCOM is cleared. When the SWSTYLE register (BCR20[7:0]) has been programmed to the ILACC compatibility mode, then this bit has no meaning and PCnet-32 controller will not set the value of this bit to ONE.
4
RCVCCOM Receive Collision Counter Over-flow Mask. If RCVCCOM is set, RCVCCO will be unable to set INTR in CSR0. RCVCCOM is set to a ONE by H_RESET or S_RESET and is not affected by STOP. When the SWSTYLE register (BCR20[7:0]) has been programmed to the ILACC compatibility mode, then this bit has no meaning and PCnet-32 controller
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will set the value of this bit to a ZERO. 3 TXSTRT Transmit Start status is set when ever PCne t- 32 co ntr oll er begins transmission of a frame. When TXSTRT is set, INTR is asserted if IENA = 1 and the mask b i t TX S T RT M ( C S R 4 b i t 2 ) i s cleared. TXSTRT is set by the MAC Unit and cleared by writing a "1", by H_RESET or S_RESET, or setting the STOP bit. Writing a "0" has no effect. 2 TXSTRTM Transmit Start Mask. If TXSTRTM is set, the TXSTRT bit in CSR4 will be masked and unable to set INTR flag in CSR0. Read/Write accessible. TXSTRTM is set to a ONE by H_RESET or S_RESET and is not affected by the STOP bit. 1 JAB Jabber Error is set when the PCnet-32 controller Twisted-pair MAU function exceeds an allowed transmission limit. Jabber is set by the T-MAU cell and can only be asserted in 10BASE-T mode. When JAB is set, INTR is asserted if IENA = 1 and the mask bit JABM (CSR4[0]) is cleared. JAB is set by the T-MAU circuit and cleared by writing a "1". Writing a "0" has no effect. JAB is also cleared by H_RESET or S_RESET or setting the STOP bit. When the SWSTYLE register (BCR20[7:0]) has been programmed to the ILACC compatibility mode, then this bit has no meaning and PCnet-32 controller will never set the value of this bit to ONE. 0 JABM Jabber Error Mask. If JABM is set, the JAB bit in CSR4 will be masked and unable to set INTR flag in CSR0. Read/Write accessible. JABM is set to a ONE by H_RESET or S_RESET and is not affected by STOP.
When the SWSTYLE register (BCR20[7:0]) has been programmed to the ILACC compatibility mode, then this bit has no meaning and PCnet-32 controller will set the value of this bit to a ZERO. CSR6: RX/TX Descriptor Table Length Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-12 TLEN
Contains a copy of the transmit encoded ring length (TLEN) field read from the initialization block during PCnet-32 controller initialization. This field is written during the PCnet-32 controller initialization routine. Read accessible only when STOP bit is set. Write operations have no effect and should not be performed. TLEN is only defined after initialization. These bits are unaffected by H_RESET, S_RESET, or STOP.
11-8
RLEN
Contains a copy of the receive encoded ring length (RLEN) read from the initialization block during PCnet-32 controller initialization. This field is wr itten dur ing the PCnet-32 controller initialization routine. Read accessible only when STOP bit is set. Write operations have no effect and should not be performed. RLEN is only defined after initialization. These bits are unaffected by H_RESET, S_RESET, or STOP.
7-0
RES
Reserved locations. Read as zero. Write operations should not be performed. Description Reserved locations. Written zeros and read as undefined. as
CSR8: Logical Address Filter, LADRF[15:0] Bit Name 31-16 RES
15-0 LADRF[15:0] Logical Address Filter, LADRF[15:0]. Defined only after the initialization block has been successfully read or a direct I/O write has been performed on this register.
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Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR9: Logical Address Filter, LADRF[31:16] Bit 31-16 Name RES Description Reserved locations. Written zeros and read as undefined. as
CSR12: Physical Address Register, PADR[15:0] Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
15-0 LADRF[31:16] Logical Address Filter, LADRF[31:16]. Defined only after the initialization block has been successfully read or a direct I/O write has been performed on this register. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR10: Logical Address Filter, LADRF[47:32] Bit 31-16 Name RES Description Reserved locations. Written zeros and read as undefined. as
15-0 PADR[15:0] Physical Address Register, PADR[15:0]. Defined only after the initialization block has been successfully read or a direct I/O write has been performed on this r e g i s t e r. T h e PA D R b i t s a r e t ra n s m i tt e d PA D R[ 0 ] f i r s t a n d PADR[47] last. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR13: Physical Address Register, PADR[31:16] Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
15-0 LADRF[47:32] Logical Address Filter, LADRF[47:32]. Defined only after the initialization block has been successfully read or a direct I/O write has been performed on this register. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR11: Logical Address Filter, LADRF[63:48] Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0
15-0 PADR[31:16] Physical Address Register, PADR[31:16]. Defined only after the initialization block has been successfully read or a direct I/O write has been performed on this r e g i s t e r. T h e PA D R b i t s a r e t ra n s m i tt e d PA D R[ 0 ] f i r s t a n d PADR[47] last. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR14: Physical Address Register, PADR[47:32] Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0
LADRF[63:48] Logical Address Filter, LADRF[63:48]. Defined only after the initialization block has been successfully read or a direct I/O write has been performed on this register. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP.
PADR[47:32]Physical Address Register, PADR[47:32]. Defined only after the initialization block has been successfully read or a direct I/O write has been performed on this r e g i s t e r. T h e PA D R b i t s a r e t ra n s m i tt e d PA D R[ 0 ] f i r s t a n d PADR[47] last. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP.
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CSR15: Mode Register Bit Name Description This register's fields are loaded during the PCnet-32 controller initialization routine with the corresponding Initialization Block values or a direct I/O write has been performed to this register. 31-16 RES 15 PROM Reserved locations. Written zeros and read as undefined. Promiscuous Mode. When PROM = "1", all incoming receive frames are accepted. Read/write accessible only when STOP bit is set. 14 DRCVBC Disable Receive Broadcast. When set, disables the PCnet-32 controller from receiving broadcast messages. Used for protocols that do not suppor t broadcast addressing, except as a function of multicast. DRCVBC is cleared by H_RESET or S_RESET (broadcast messages will be received) and is unaffected by STOP. Read/write accessible only when STOP bit is set. 13 DRCVPA Disable Receive Physical Address. When set, the physical address detection (Station or node ID) of the PCnet-32 controller will be disabled. Frames addressed to the nodes individual physical address will not be recognized (although the frame may be accepted by the EADI mechanism). Read/write accessible only when STOP bit is set. 12 DLNKTST Disable Link Status. When DLNKTST = "1", monitoring of Link Pulses is disabled. When DLNKTST = "0", monitoring of Link Pulses is enabled. This bit only has meaning when the 10BASE-T network interface is selected. Read/write accessible only when STOP bit is set. 11 DAPC Disable Automatic Polarity Correction. When DAPC = "1", the 10BASE-T receive polarity reversal algorithm is disabled. Likewise, TSEL 9 as
when DAPC = "0", the polar ity reversal algorithm is enabled. This bit only has meaning when the 10BASE-T network interface is selected. Read/write accessible only when STOP bit is set. 10 MENDECL MENDEC Loopback Mode. See the descr iption of the LOOP bit in CSR15. Read/write accessible only when STOP bit is set. LRT/TSEL Low Receive Threshold (T-MAU Mode only) Transmit Mode Select (AUI Mode only) LRT Low Receive Threshold. When LRT = "1", the inter nal twisted pair receive thresholds are reduced by 4.5 dB below the standard 10BASE-T value (approximately 3/5) and the unsquelch threshold for the RXD circuit will be 180-312 mV peak. When LRT = "0", the unsquelch threshold for the RXD circuit will be the standard 10BASE-T value, 300 - 520 mV peak. In either case, the RXD circuit post squelch threshold will be one half of the unsquelch threshold. This bit only has meaning when the 10BASE-T network interface is selected. Read/write accessible only when S TO P b i t i s s e t . C l e a r e d b y H_RESET or S_RESET and is unaffected by STOP. TSEL Transmit Mode Select. TSEL controls the levels at which the AUI drivers rest when the AUI transmit port is idle. When TSEL = 0, DO+ and DO- yield "zero" differential to operate transformer coupled loads (Ethernet 2 and 802.3). When TSEL = 1, the DO+ idles at a higher value with respect to DO-, yielding a logical HIGH state (Ethernet 1). This bit only has meaning when the AUI network interface is selected.
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Read/write accessible only when S TO P b i t i s s e t . C l e a r e d b y H_RESET or S_RESET and is unaffected by STOP. 8-7 PORTSEL[1:0] Port Select bits allow for software controlled selection of the network medium. PORTSEL settings of AUI and 10BASE-T are ignored when the ASEL bit of BCR2 (bit 1) has been set to ONE. The network port configuration is shown in Table 41.
Table 41. Network Port Configuration.
PORTSEL[1:0] 0X 0X 00 01 10 11 ASEL (BCR2[1]) 1 1 0 0 X X Link Status (of 10BASE-T) Fail Pass X X X X Network Port AUI 10BASE-T AUI 10BASE-T GPSI Reserved
will ultimately result. If FCOLL = "0", the Force Collision logic will be disabled. Read/write accessible only when STOP bit is set. 3 DXMTFCS Disable Transmit CRC (FCS). When DXMTFCS = 0, the transmitter will generate and append a FCS to the transmitted frame. When DXMTFCS = 1, the FCS logic is allocated to the receiver and no FCS is generated or sent with the transmitted frame. DXMTFCS is overridden when ADD_FCS is set in TMD1. See also the ADD_FCS bit in TMD1. If DXMTFCS is set and ADD_FCS is clear for a particular frame, no FCS will be generated. The value of ADD_FCS is valid only when STP is s e t . I f A D D _ F C S i s s e t fo r a p a r t i c u l a r f r a m e, t h e s t a t e o f DXMTFCS is ignored and a FCS will be appended on that frame by the transmit circuitry. In loopback mode, this bit determines if the transmitter appends FCS or if the receiver checks the FCS. This bit was called DTCR in the LANCE (Am7990). Read/write accessible only when STOP bit is set. 2 LOOP Loopback Enable allows PCnet-32 controller to operate in full duplex mode for test pur poses. When LOOP = "1", loop-back is enabled. In combination with INTL and M E N D E C L , va r i o u s l o o p b a c k modes are defined in Table 42.
Refer to the section on General Purpose Serial Interface for detailed information on accessing GPSI. Read/write accessible only when S TO P b i t i s s e t . C l e a r e d b y H_RESET or S_RESET and is unaffected by STOP. 6 INTL Internal Loopback. See the description of LOOP, CSR15-2. Read/write accessible only when STOP bit is set. 5 DRTY Disable Retry. When DRTY = "1", PCnet-32 controller will attempt only one transmission. If DRTY = "0", PCnet-32 controller will attempt 16 retry attempts before signaling a retry error. DRTY is defined when the initialization block is read. Read/write accessible only when STOP bit is set. 4 FCOLL Force Collision. This bit allows the collision logic to be tested. PCnet-32 c o n t r o l l e r mu s t b e i n i n t e r n a l loopback for FCOLL to be valid. If FCOLL = "1", a collision will be fo r c e d during loop-back transmission attempts. A Retry Error AM79C965A
Table 42. Loopback Modes.
LOOP 0 1 1 1 INTL X 0 1 1 MENDECL X X 0 1 Loopback Mode Non-Loopback External Loopback Internal Loopback Include MENDEC Internal Loopback Exclude MENDEC
Read/write accessible only when STOP bit is set. LOOP is cleared by
135
H_RESET or S_RESET and is unaffected by the STOP bit. 1 DTX Disable Transmit results in PCnet-32 controller not accessing the Tr a n s m i t D e s c r i p t o r Ri n g a n d therefore no transmissions are attempted. DTX = "0", will set TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is asserted. Read/write accessible only when STOP bit is set. 0 DRX Disable Receiver results in PCnet-32 controller not accessing the Receive Descriptor Ring and therefore all receive frame data are ignored. DRX = "0", will set RXON bit (CSR0 bit 5) if STRT (CSR0 bit 1) is asserted. Read/write accessible only when STOP bit is set. CSR16: Initialization Block Address Lower Bit Name Description This register is an alias of the location CSR1. Accesses to/from this register are equivalent to access to CSR1. 31-16 RES 15-0 IADR Reserved locations. Written zeros and read as undefined. as
Read/Write accessible only when t h e S TO P b i t i n C S R 0 i s s e t . Unaffected by RESET. CSR18: Current Receive Buffer Address Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 CRBA
Contains the lower 16 bits of the current receive buffer address at which the PCnet-32 controller will store incoming frame data. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP.
CSR19: Current Receive Buffer Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 CRBA
Contains the upper 16 bits of the current receive buffer address at which the PCnet-32 controller will store incoming frame data. Read/write accessible only when STOP bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP.
Lower 16 bits of the address of the Initialization Block. This register is an alias of CSR1. Whenever this register is written, CSR1 is updated with CSR16's contents. Read/Write accessible only when t h e S TO P b i t i n C S R 0 i s s e t . Unaffected by RESET.
CSR20: Current Transmit Buffer Address Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 CXBA
Contains the lower 16 bits of the current transmit buffer address from which the PCnet-32 controller is transmitting. Read/write accessible only when STOP bit is set.
CSR17: Initialization Block Address Upper Bit Name Description This register is an alias of the location CSR2. Accesses to/from this register are equivalent to access to CSR2. 31-16 RES 15-0 IADR Reserved locations. Written zeros and read as undefined. as 15-0 CXBA
CSR21: Current Transmit Buffer Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
Upper 16 bits of the address of the Initialization Block. This register is an alias of CSR2. Whenever this register is written, CSR2 is updated with CSR17's contents.
Contains the upper 16 bits of the current transmit buffer address from which the PCnet-32 controller is transmitting. Read/write accessible only when STOP bit is set.
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CSR22: Next Receive Buffer Address Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 NRBA
CSR27: Next Receive Descriptor Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 NRDA
Contains the lower 16 bits of the next receive buffer address to which the PCnet-32 controller will store incoming frame data. Read/write accessible only when STOP bit is set.
Contains the upper 16 bits of the next RDRE address pointer. Read/write accessible only when STOP bit is set.
CSR28: Current Receive Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRDA Contains the lower 16 bits of the current RDRE address pointer. Read/write accessible only when STOP bit is set. CSR29: Current Receive Descriptor Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 CRDA
CSR23: Next Receive Buffer Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 NRBA
Contains the upper 16 bits of the next receive buffer address to which the PCnet-32 controller will store incoming frame data. Read/write accessible only when STOP bit is set.
CSR24: Base Address of Receive Ring Lower Bit 31-16 15-0 Name RES BADR Description Reserved locations. Written zeros and read as undefined. as
Contains the upper 16 bits of the current RDRE address pointer. Read/write accessible only when STOP bit is set.
Contains the lower 16 bits of the base address of the Receive Ring. Read/write accessible only when STOP bit is set. Bit Name
CSR30: Base Address of Transmit Ring Lower Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 BADX
CSR25: Base Address of Receive Ring Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 BADR
Contains the lower 16 bits of the base address of the Transmit Ring. Read/write accessible only when STOP bit is set.
Contains the upper 16 bits of the base address of the Receive Ring. Read/write accessible only when STOP bit is set. Bit Name
CSR31: Base Address of Transmit Ring Upper Description Reserved locations. written as zero. Read and 31-16 RES 15-0 BADX
CSR26: Next Receive Descriptor Address Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 NRDA
Contains the upper 16 bits of the base address of the Transmit Ring. Read/write accessible only when STOP bit is set.
Contains the lower 16 bits of the next RDRE address pointer. Read/write accessible only when STOP bit is set. Bit Name
CSR32: Next Transmit Descriptor Address Lower Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
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15-0
NXDA
Contains the lower 16 bits of the next TDRE address pointer. Read/write accessible only when STOP bit is set.
15-0
NNRDA
Contains the upper 16 bits of the next next receive descriptor address pointer. Read/write accessible only when STOP bit is set.
CSR33: Next Transmit Descriptor Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 NXDA
CSR38: Next Next Transmit Descriptor Address Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 NNXDA
Contains the upper 16 bits of the next TDRE address pointer. Read/write accessible only when STOP bit is set.
Contains the lower 16 bits of the next next transmit descriptor address pointer. Read/write accessible only when STOP bit is set.
CSR34: Current Transmit Descriptor Address Lower Bit Name Description Reserved locations. written as zero. Read and 31-16 RES 15-0 CXDA
CSR39: Next Next Transmit Descriptor Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 NNXDA
Contains the lower 16 bits of the current TDRE address pointer. Read/write accessible only when STOP bit is set.
CSR35: Current Transmit Descriptor Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 CXDA
Contains the upper 16 bits of the next next transmit descriptor address pointer. Read/write accessible only when STOP bit is set.
CSR40: Current Receive Status and Byte Count Lower Bit Name Description Reserved locations. Written zeros and read as undefined. Reserved locations. written as zero. Read as and 31-16 RES 15-12 RES 11-0 CRBC
Contains the upper 16 bits of the current TDRE address pointer. Read/write accessible only when STOP bit is set.
CSR36: Next Next Receive Descriptor Address Lower Bit 31-16 15-0 Name RES NNRDA Description Reserved locations. Written zeros and read as undefined. as
Current Receive Byte Count. This field is a copy of the BCNT field of RMD 2 of the current receive descriptor. Read/write accessible only when STOP bit is set.
Contains the lower 16 bits of the next next receive descriptor address pointer. Read/write accessible only when STOP bit is set.
CSR41: Current Receive Status and Byte Count Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-8 CRST
CSR37: Next Next Receive Descriptor Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
Current Receive Status. This field is a copy of bits 15:8 of RMD1 of the current receive descriptor.
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Read/write accessible only when STOP bit is set. 7-0 RES Reserved locations. written as zero. Read and
15-8
NRST
Next Receive Status. This field is a copy of bits 15:8 of RMD1 of the next receive descriptor. Read/write accessible only when STOP bit is set.
CSR42: Current Transmit Status and Byte Count Lower Bit Name Description Reserved locations. Written zeros and read as undefined. Reserved locations. written as zero. Read as and 31-16 RES 15-12 RES 11-0 CXBC
7-0
RES
Reserved locations. written as zero. Description
Read
and
CSR46: Poll Time Counter Bit Name 31-16 RES 15-0 POLL Reserved locations. Written zeros and read as undefined. as
Current Transmit Byte Count. This field is a copy of the BCNT field of TMD2 of the current transmit descriptor. Read/write accessible only when STOP bit is set.
Poll Time Counter. This counter is i n c r em e n t e d by th e P C n e t- 3 2 controller microcode and is used to trigger the descriptor ring polling operation of the PCnet-32 controller. Read/write accessible only when STOP bit is set.
CSR43: Current Transmit Status and Byte Count Upper Bit 31-16 15-8 Name RES CXST Description Reserved locations. Written zeros and read as undefined. as
CSR47: Polling Interval Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0
Current Transmit Status. This field is a copy of bits 15:8 of TMD1 of the current transmit descriptor. Read/write accessible only when STOP bit is set.
7-0
RES Reserved locations. Read and written as zero.
CSR44: Next Receive Status and Byte Count Lower Bit 31-16 Name RES Description Reserved locations. Written zeros and read as undefined. Reserved locations. written as zero. Read as and
POLLINT Polling Interval. This register contains the time that the PCnet-32 controller will wait between successive polling operations. The POLLINT value is expressed as the two's complement of the desired interval, where each bit of POLLINT represents 1 BCLK period of time (486 and VL-Bus modes; 2 BCLK 38 6 mo de) . P O LLINT[ 3:0] ar e ignored. (POLLINT[16] is implied to be a one, so POLLINT[15] is significant, and does not represent the sign of the two's complement POLLINT value.) The default value of this register is 0000. This corresponds to a polling interval of 65,536 BCLK periods (486 and VL-Bus modes; 131,072 BCLK 386 mode). The POLLINT value of 0000 is created during the microcode initialization routine, and therefore might not be seen when reading CSR47 after H_RESET or S_RESET. If the user desires to program a value for POLLINT other than the default, then the correct procedure is to first set INIT only in CSR0. Then, when the initialization 139
15-12 RES 11-0 NRBC
Next Receive Byte Count. This field is a copy of the BCNT field of RMD2 of the next receive descriptor. Read/write accessible only when STOP bit is set.
CSR45: Next Receive Status and Byte Count Upper Bit 31-16 Name RES Description Reserved locations. Written zeros and read as undefined. as
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sequence is complete, the user must set STOP in CSR0. Then the user may write to CSR47 and then set STRT in CSR0. In this way, the default value of 0000 in CSR47 will be overwritten with the desired user value. If the user does NOT use the standard initialization procedure (standard implies use of an initialization block in memory and setting the INIT bit of CSR0), but instead, chooses to write directly to ea ch of th e r eg is te rs th at a r e involved in the INIT operation, then it is imperative that the user also write 0000 0000 to CSR47 as part of the alternative initialization sequence. Read/write accessible only when STOP bit is set. CSR48: Temporary Storage 2 Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP2
15-0
TMP3
Upper 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR52: Temporary Storage 4 Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP4
Lower 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR53: Temporary Storage 4 Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP4
Upper 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR54: Temporary Storage 5 Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP5
Lower 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR49: Temporary Storage 2 Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as Bit Name 31-16 RES 15-0 TMP2
Lower 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR55: Temporary Storage 5 Upper Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP5
Upper 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR50: Temporary Storage 3 Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as Bit Name 31-16 RES 15-0 TMP3
Upper 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR56: Temporary Storage 6 Lower Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP6
Lower 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR51: Temporary Storage 3 Upper Bit Name Description Reserved locations. Written as zeros and read as undefined. 31-16 RES
Lower 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
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CSR57: Temporary Storage 6 Upper Bit 31-16 15-0 Name RES TMP6 Description Reserved locations. Written zeros and read as undefined. as
The value of SSIZE32 is determined by the PCnet-32 controller. SSIZE32 is read only by the host. The PCnet-32 controller uses the setting of the Software Style register (BCR20, bits 7-0) to determine the value for this bit. SSIZE32 is cleared by H_RESET or S_RESET and is not affected by STOP. If SSIZE32 is reset, then bits IADR[31:24] of CSR2 will be used to generate values for the upper 8 bits of the 32 bit address bus during master accesses initiated by the PCnet-32 controller. This action is required, since the 16-bit software structures specified by the SSIZE32=0 setting will yield only 24 b i t s o f a d d r e s s fo r P C n e t - 3 2 controller bus master accesses. If SSIZE32 is set, then the software structures that are common to the PCnet-32 controller and the host system will supply a full 32 bits for each address pointer that is needed by the PCnet-32 controller for performing master accesses. The value of the SSIZE32 bit has no effect on the drive of the upper 8 address pins. The upper 8 address pins are always driven, regardless of the state of the SSIZE32 bit. Note that the setting of the SSIZE32 bit has no effect on the defined width for I/O resources. I/O resource width is determined by the state of the DWIO bit. 7-0 SWSTYLE Software Style register. The value in this register determines the "style" of I/O and memory resources that are used by the PCnet-32 controller. The S/W resource style selection will affect the interpretation of a few bits within the CSR space and the width of the descriptors and initialization block. See Table 43. All PCnet-32 controller CSR bits and BCR bits and all descriptor, buffer and initialization block entries not cited in the table above ar e unaffected by the Software Style selection and are therefore always fully functional as specified in the BCR and CSR sections.
Upper 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR58: Software Style Bit Name Description This register is an alias of the location BCR20. Accesses to/from this r egister are equivalent to accesses to BCR20. 31-10 RES 9 Reserved locations. Written zeros and read as undefined. as
CSRPCNET CSR PCnet-ISA configuration bit. When set, this bit indicates that the PCnet-32 controller register bits of CSR4 and CSR3 will map directly to the CSR4 and CSR3 bits of the PCnet-ISA (Am79C960) device. When cleared, this bit indicates that PCnet-32 controller register bits of CSR4 and CSR3 will map directly to the CSR4 and CSR3 bits of the ILACC (Am79C900) device. The value of CSRPCNET is deter mined by the PCnet-32 controller. CSRPCNET is read only by the host. The PCnet-32 controller uses the setting of the Software Style register (BCR20[7:0]/CSR58[7:0]) to determine the value for this bit. CSRPCNET is set to a ONE by H_RESET or S_RESET and is not affected by STOP.
8
SSIZE32 Software Size 32 bits. When set, this bit indicates that the PCnet-32 controller utilizes AMD 79C900 (ILACC) software structures. In particular, Initialization Block and Transmit and Receive descriptor bit maps are affected. When cleared, this bit indicates that the PCnet-32 controller utilizes AMD PCnet-ISA software str uctures. Note: Regardless of the setting of SSIZE32, the Initialization Block must always begin on a double-word boundary. AM79C965A
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Read/write accessible only when STOP bit is set.
The SWSTYLE register will contain the value 00h following H_RESET or S_RESET and will be unaffected by STOP.
Table 43. Software Resource Style Selection
SWSTYLE[7:0] (Hex) 00 01 Style Name LANCE/ PCnet-ISA ILACC CSRPCNET 1 0 SSIZE32 0 1 Altered Bit Interpretations ALL CSR4 bits will function as defined in the CSR4 section. TMD1[29] functions as ADD_FCS CSR4[9:8], CSR4[5:4] and CSR4[1:0] will have no function, but will be writeable and readable. CSR4[15:10], CSR4[7:6] and CSR4[3:2] will function as defined in the CSR4 section. TMD1[29] becomes NO_FCS. ALL CSR4 bits will function as defined in the CSR4 section. TMD1[29] functions as ADD_FCS Undefined
02 All other combinations
PCnet-32 Reserved
1 Undefined
1 Undefined
CSR59: IR Register Bit Name Description Reserved locations. Written zeros and read as undefined. Contains the value 0105. This register always contains the same value. It is not writable. Read accessible only when STOP bit is set. CSR60: Previous Transmit Descriptor Address Lower Bit 31-16 15-0 Name RES PXDA Description Reserved locations. Written zeros and read as undefined. as 11-0 PXBC as 31-16 RES 15-0 IRREG
Read/write accessible only when STOP bit is set. CSR62: Previous Transmit Status and Byte Count Lower Bit Name Description Reserved locations. Written zeros and read as undefined. Reserved locations. written as zero. Read as and 31-16 RES 15-12 RES
Accessible only when STOP bit is set. Previous Transmit Byte Count. This field is a copy of the BCNT field of TMD2 of the previous transmit descriptor. Read/write accessible only when STOP bit is set. CSR63: Previous Transmit Status and Byte Count Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-8 as PXST
Contains the lower 16 bits of the previous TDRE address pointer. PCnet-32 controller has the capability to stack multiple transmit frames. Read/write accessible only when STOP bit is set.
CSR61: Previous Transmit Descriptor Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. 31-16 RES 15-0 PXDA
Previous Transmit Status. This field is a copy of bits 15:8 of TMD1 of the previous transmit descriptor. Read/write accessible only when STOP bit is set.
Contains the upper 16 bits of the previous TDRE address pointer. PCnet-32 controller has the capability to stack multiple transmit frames.
7-0
RES
Reserved locations. written as zero.
Read
and
Accessible only when STOP bit is set.
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CSR64: Next Transmit Buffer Address Lower Bit 31-16 15-0 Name RES NXBA Description Reserved locations. Written zeros and read as undefined. as
31-16 RES 15-8 NXST
Reserved locations. Written zeros and read as undefined.
as
Next Transmit Status. This field is a copy of bits 15:8 of TMD1 of the next transmit descriptor. Read/write accessible only when STOP bit is set.
Contains the lower 16 bits of the next transmit buffer address from which the PCnet-32 controller will transmit an outgoing frame. Read/write accessible only when STOP bit is set.
7-0
RES
Reserved locations. written as zero.
Read
and
CSR65: Next Transmit Buffer Address Upper Bit 31-16 15-0 Name RES NXBA Description Reserved locations. Written zeros and read as undefined. as
Accessible only when STOP bit is set. CSR68: Transmit Status Temporary Storage Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 XSTMP
Contains the upper 16 bits of the next transmit buffer address from which the PCnet-32 controller will transmit an outgoing frame. Read/write accessible only when STOP bit is set.
Lower 16 bits of a Transmit Status Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR66: Next Transmit Status and Byte Count Lower Bit Name Description Reserved locations. Written zeros and read as undefined. Reserved locations. written as zero. Read as 31-16 RES 15-12 RES
CSR69: Transmit Status Temporary Storage Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 and XSTMP
Transmit Status Temporary Storage location. Read/write accessible only when STOP bit is set.
Accessible only when STOP bit is set. 11-0 NXBC Next Transmit Byte Count. This field is a copy of the BCNT field of TMD2 of the next transmit descriptor.
CSR70: Temporary Storage Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP8
Read/write accessible only when STOP bit is set. CSR67: Next Transmit Status and Byte Counter Upper Bit Name Description
Lower 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
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CSR71: Temporary Storage Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 TMP8
register can be manually altered. the actual receive ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. Read/write accessible only when STOP bit is set. CSR78: Transmit Ring Length Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
Upper 16 bits of a Temporary Storage location. Read/write accessible only when STOP bit is set.
CSR72: Receive Ring Counter Bit 31-16 15-0 Name RES RCVRC Description Reserved locations. Written zeros and read as undefined. as
15-0
XMTRL
Receive Ring Counter location. Contai ns a Two 's c ompl emen t binary number used to number the current receive descriptor. This counter inter prets the value in CSR76 as pointing to the first descriptor. A counter value of zero corresponds to the last descriptor in the ring. Read/write accessible only when STOP bit is set.
Transmit Ring Length. Contains the two's complement of the transmit descriptor ring length. This register is initialized during the PCnet-32 controller initialization routine based on the value in the TLEN field of the initialization block. However, this register can be manually altered. The actual transmit ring length is defined by the current value in this register. The ring length can be defined as any value from 1 to 65535. Read/write accessible only when STOP bit is set.
CSR74: Transmit Ring Counter Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 XMTRC
CSR80: Burst and FIFO Threshold Control Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-14 RES
Transmit Ring Counter location. Contai ns a Two 's c ompl emen t binary number used to number the current transmit descriptor. This counter inter prets the value in CSR78 as pointing to the first descriptor. A counter value of zero corresponds to the last descriptor in the ring. Read/write accessible only when STOP bit is set.
Reserved locations. Read as ones and written as zero.
CSR76: Receive Ring Length Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 RCVRL
Receive Ring Length. Contains the two's complement of the receive descriptor ring length. This register is initialized during the PCnet-32 controller initialization routine based on the value in the RLEN field of the initialization block. However, this
13-12 RCVFW[1:0] Receive FIFO Watermark. RCVFW controls the point at which receive DMA is requested in relation to the number of received bytes in the receive FIFO. RCVFW specifies the number of bytes which must be present (once the frame has been ve r ifi ed as a no n- r unt) b efor e receive DMA is requested. Note however that in order for receive DMA to be performed for a new frame, at least 64 bytes must have been received. This effectively avoids having to react to receive frames which are runts or suffer a collision during the slot time (512 bit times). If the Runt Packet Accept feature is enabled, receive DMA will be requested as soon as either the RCVFW threshold is reached, or a complete valid receive frame is
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detected (regardless of length). RCVFW is set to a value of 10 (64 bytes) after H_RESET or S_RESET and is unaffected by STOP.
XMTSP[1:0] 00 01 10 11
Bytes Written 4 16 64 112
RCVFW[1:0] 00 01 10 11
Bytes Received 16 32 64 Reserved
9-8
Read/write accessible only when
STOP bit is set.
Certain combinations of watermark programming and LINBC (BCR18[20 ] ) p r o g r a m m i n g m ay c r e a t e situations where no linear bursting is possible, or where the FIFO may be excessively read or excessively written. Such combinations are declared as illegal. Combinations of watermark settings and LINBC settings must obey the following relationship: watermark (in bytes) S LINBC (in bytes) Combinations of watermark and LINBC settings that violate this rule may cause unexpected behavior. 11-10 XMTSP[1:0]Transmit Start Point. XMTSP controls the point at which prea m bl e t r a n s m i s s i o n a t t e m p t s commence in relation to the number of bytes written to the transmit FIFO for the current transmit frame. When the entire frame is in the FIFO, transmission will start regardless of the value in XMTSP. XMTSP is given a valu e of 1 0 ( 64 byt es ) a fter H_RESET or S_RESET and is unaffected by STOP. Regardless of XMTSP, the FIFO will not internally over write its data until at least 64 bytes (or the entire frame if <64 bytes) have been transmitted onto the network. This ensures that for c o l l i s i on s wi t h i n th e s l o t t i m e window, transmit data need not be rewritten to the transmit FIFO, and retries will be handled autonomously by the MAC. This bit is read/write accessible only when the STOP bit is set.
XMTFW[1:0] Transmit FIFO Watermark. XMTFW specifies the point at which transmit DMA stops, based upon the number of write cycles that could be perfor med to the transmit FIFO without FIFO overflow. Transmit DMA is allowed at any time when the number of write cycles specified by SMTFW could be executed without causing transmit FIFO overflow. XMTFW is set to a value of 00b (8 cycles) after H_RESET or S_RESET and is unaffected by STOP. Read/write accessible only when STOP bit is set.
XMTFW[1:0] 00 01 10 11
Write Cycles 8 16 32 Reserved
Certain combinations of watermark programming and LINBC programming may create situations where no linear bursting is possible, o r w h e r e t h e F I F O m ay b e excessively read or excessively written. Such combinations are declared as illegal. Combinations of watermark settings and LINBC settings must obey the following relationship: watermark (in bytes) S LINBC (in bytes) Combinations of watermark and LINBC settings that violate this rule may cause unexpected behavior. 7-0 DMACR[7:0] DMA Cycle Register. This register contains the maximum allowable number of transfers to system memory that the Bus Interface will perform during a single DMA cycle. The Cycle Register is not used to limit the number of transfers during Descriptor transfers. A value of zero will be interpreted as one transfer.
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During H_RESET or S_RESET a value of 16 is loaded in the BURST register. If the DMAPLUS bit in CSR4 is set, the DMA Cycle Register is disabled. When the ENTST bit in CSR4 is set, all writes to this register will automatically perform a decrement cycle. When the Cycle Register times out in the middle of a linear burst, the linear burst will continue until a legal starting address is reached, and then the PCnet-32 controller will relinquish the bus. Therefore, if linear bursting is enabled, and the user wishes the PCnet-32 controller to limit bus activity to desired_max transfers, then the Cycle Register should be programmed to a value of: Burst count setting = (desired_ max D I V ( l e n g t h o f l i n e a r bu r s t i n transfers) x length of linear burst in transfers where DIV is the operation that yields the INTEGER portion of the operation. Note: If either Linear Burst Write is enabled, the value has to be greater than or equal to 4. Read/write accessible only when the STOP bit is set. CSR82: Bus Activity Timer Bit 31-16 15-0 Name RES Description Reserved locations. Written zeros and read as undefined. as
register is undefined until written. When the ENTST bit in CSR4 is set, all writes to this register will automatically perform a decrement cycle. If the user has NOT enabled the Linear Burst function and wishes the PCnet-32 controller to limit bus activity to MAX_TIME s, then the Burst Timer should be programmed to a value of: MAX_TIME- [(11 + 4w) x (BCLK period)], where w = wait states. If the user has enabled the Linear Burst function and wis hes the PCnet-32 controller to limit bus activity to MAX_TIME s, then the Burst Timer should be programmed to a value of: MAX_TIME- [((3+lbs) x w + 10 + lbs) x (BCLK period)], where w = wait states and lbs = li near bur s t s ize in nu mber of transfers per sequence. This is because the PCnet-32 controller may use as much as one " l i n e a r bu r s t s i z e " p l u s t h r e e transfers in order to complete the linear burst before releasing the bus. As an example, if the linear burst si ze is four trans fer s, and the number of wait states for the system memory is two, and the BCLK period is 30 ns and the MAX time allowed on the bus is 3 s, then the Burst Timer should be programmed for: MAX_TIME- [((3+lbs) x w + 10 + lbs) x (BCLK period)], 3 mS - [(3 + 4) x 2 +10 + 4) x (30 ns)] = 3 mS - (28 x 30 ns) = 3 - 0.84 mS = 2.16 mS. Then, if the PCnet-32 controller's Bus ActivityTimer times out after 2.16 s when the PCnet-32 controller has completed all but the last three transfers of a linear burst, the PCnet-32 controller may take as much as 0.84 s to complete the bursts and release the bus. The bus release will occur at 2.16 + 0.84 = 3 ms.
DMABAT Bus Activity Timer Register. If the TIMER bit in CSR4 is set, this register contains the maximum a l l owa bl e t i m e t h a t P C n e t - 3 2 controller will take up on the system bus during FIFO data transfers for a single DMA cycle. The Bus Activity Timer Register does not limit the n u m b e r o f t r a n s fe r s d u r i n g Descriptor transfers. The DMABAT value is interpreted as an unsigned number with a resolution of 0.1 s. For instance, a value of 51 s would be programmed with a value of 510. If the TIMER bit in CSR4 is set, DMABAT is enabled and must be initialized by the user. The DMABAT
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A value of zero will in the DMABAT register with the TIMER bit in CSR4 set to ONE will produce single linear burst sequences per bus master period when programmed for linear burst mode, and will yield sets of th r e e tra n s fer s wh e n no t pr o grammed for linear burst mode. The Bus Activity Timer is set to a value of 00h after H_RESET or S_RESET and is unaffected by STOP. Read/write accessible only when STOP bit is set. CSR84: DMA Address Lower Bit 31-16 15-0 Name RES DMABA Description Reserved locations. Written zeros and read as undefined. DMA Address Register. This register contains the lower 16 bi t s o f th e ad d r e s s of s y s t em memory for the current DMA cycle. The Bus Interface Unit controls the Address Register by issuing increment commands to increment the memory address for sequential operations. The DMABA register is undefined until the first PCnet-32 controller DMA operation. When the ENTST bit in CSR4 is set, all writes to this register will automatically perform an increment cycle. Read/write accessible only when STOP bit is set. CSR85: DMA Address Upper Bit Name Description Reserved locations. Written zeros and read as undefined. DMA Address Register. This register contains the upper 16 bi t s o f th e ad d r e s s of s y s t em memory for the current DMA cycle. The Bus Interface Unit controls the Address Register by issuing increment commands to increment the memory address for sequential operations. The DMABA register is undefined until the first PCnet-32 controller DMA operation. When the ENTST bit in CSR4 is set, all writes to this register will automatically perform an increment cycle. as 31-16 RES 15-0 DMABA as
Read/write accessible only when STOP bit is set. CSR86: Buffer Byte Counter Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-12 RES 11-0 DMABC
Reserved, Read and written with ones. DMA Byte Count Register. Contains a Two's complement binary number of the current size of the remaining transmit or receive buffer in bytes. This register is incremented by the Bus Interface Unit. The DMABC register is un d efi n ed un ti l wr it te n. W he n ENTST (CSR4.15) is asserted, all writes to this register will automatically perform an increment cycle. Read/write accessible only when STOP bit is set.
CSR88: Chip ID Lower Bit Name Description This register is exactly the same as the Chip ID register in the JTAG description. 31 - 28 Version. This 4-bit pattern is silicon-revision dependent.
27 - 12 Part number. The 16-bit code for the PCnet-32 controller is 0010 0100 0011 0000b. 11 - 1 Manufacturer ID. The 11-bit manufacturer code for AMD is 00000000001b. This code is per the JEDEC Publication 106-A. Always a logic 1. Name Description The lower 16 bits of this register are exactly the same as the upper 16 bits of the Chip ID register in the JTAG description, which are exactly the same as the upper 16 bits of CSR88. 31 - 16 15 - 12 Reserved locations. undefined. Read as
0 Bit
CSR89: Chip ID Upper
Version. This 4-bit pattern is siliconrevision dependent.
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11 - 0
Upper 12 bits of the PCnet-32 controller part number, i.e. 0010 0100 0011b. Name RES RCON Description Reserved locations. Written zeros and read as undefined. as
CSR97: Bus Interface Scratch Register 0 Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 S CR0
CSR92: Ring Length Conversion Bit 31-16 15-0
Ring Length Conversion Register. This register performs a ring length conversion from an encoded value as found in the initialization block to a Two's complement value used for internal counting. By writing bits 1512 with an encoded ring length, a Two's complemented value is read. The RCON register is undefined until written. Read/write accessible only when STOP bit is set.
This register is shared between the Buffer Management Unit and the Bus Interface Unit. All Descriptor Data communications between the BIU and BMU are written and read through SCR0 and SCR1 registers. The SCR0 register is undefined until written. Read/write accessible only when STOP bit is set.
CSR98: Bus Interface Scratch Register 1 Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 SCR1
CSR94: Transmit Time Domain Reflectometry Count Bit Name Description Reserved locations. Written zeros and read as undefined. Reserved locations. written as zero. Read as and 31-16 RES 15-10 RES 9-0
This register is shared between the Buffer Management Unit and the Bus Interface Unit. All Descriptor Data communications between the BIU and BMU are written and read through SCR0 and SCR1 registers. Read/write accessible only when STOP bit is set.
XMTTDR Time Domain Reflectometry reflects the state of an internal counter that counts from the star t of transmission to the occurrence of loss of carrier. TDR is incremented at a rate of 10 MHz. Read accessible only when STOP bit is set. Write operations are ignored. XMTTDR is cleared by H_RESET or S_RESET.
CSR99: Bus Interface Scratch Register 1 Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 SCR1
CSR96: Bus Interface Scratch Register 0 Lower Bit 31-16 15-0 Name RES SCR0 Description Reserved locations. Written zeros and read as undefined. as
This register is shared between the Buffer Management Unit and the Bus Interface Unit. All Descriptor Data communications between the BIU and BMU are written and read through SCR0 and SCR1 registers. Read/write accessible only when STOP bit is set.
CSR100: Bus Time-Out Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0
This register is shared between the Buffer Management Unit and the Bus Interface Unit. All Descriptor Data communications between the BIU and BMU are written and read through SCR0 and SCR1 registers. The SCR0 register is undefined until written. Read/write accessible only when STOP bit is set.
MERRTO This register contains the value of the longest allowable bus latency (interval between assertion of HOLD and assertion of HLDA) that a slave device may insert into a PCnet-32 controller master transfer. If this value of bus latency is exceeded,
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then a MERR will be indicated in CSR0, bit 11, and an interrupt may be generated, depending upon the setting of the MERRM bit (CSR3, bit 11) and IENA bit (CSR0[6]). The value in this register is interpreted as a number of XTAL12 clock periods. (i.e. the value in this regis ter is given in 0.1 ms increments.) For example, the value 0200h (512 decimal) will cause a MERR to be indicated after 51.2 s of bus latency. A value of zero will allow an infinitely long bus latency. i.e. a value of zero will never give a bus time-out error. A non-zero value is interpreted as an unsigned number of BCLK cycles. This register is set to 0200 by H_RESET or S_RESET and is unaffected by STOP. Read/write accessible only when STOP bit is set. CSR104: SWAP Register Lower Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 SWAP Bit Name Bit Name
the lower 16 bits and CSR105 holds the upper 16 bits. Read/write accessible only when STOP bit is set. CSR108: Buffer Management Scratch Lower Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 BMSCR
The Buffer Management Scratch register is used for assembling Receive and Transmit Status. This register is also used as the primary scan register fo r B u f fe r Management Test Modes. BMSCR register is undefined until written. Read/write accessible only when STOP bit is set.
CSR109: Buffer Management Scratch Upper Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 BMSCR
This register performs word and byte swapping depending upon if 3 2 - b i t o r 1 6 - b i t i n te r n a l wr i t e operations are perfor med. This register is used internally by the BIU/ BMU as a word or byte swapper. The register is externally accessible for test reasons only. CSR104 holds the lower 16 bits and CSR105 holds the upper 16 bits. Read/write accessible only when STOP bit is set.
The Buffer Management Scratch register is used for assembling Receive and Transmit Status. This register is also used as the primary scan register fo r B u f fe r Management Test Modes. BMSCR register is undefined until written. Read/write accessible only when STOP bit is set.
CSR112: Missed Frame Count Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 MFC
Missed Frame Count. Indicates the number of missed frames. MFC will roll over to a count of zero from the value 65535. The MFCO bit of CSR4 (bit 8) will be set each time that this occurs. This register is always readable and is cleared by H_RESET or S_RESET or STOP. A write to this register performs an increment when the ENTST bit in CSR4 is set.
CSR105: SWAP Register Upper Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15-0 SWAP
This register performs word and byte swapping depending upon if 3 2 - b i t o r 1 6 - b i t i n te r n a l wr i t e operations are perfor med. This register is used internally by the BIU/ BMU as a word or byte swapper. The register is externally accessible for test reasons only. CSR104 holds
CSR114: Receive Collision Count Bit Name Description
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31-16 RES 15-0 RCC
Reserved locations. Written zeros and read as undefined.
as
CSR124: Buffer Management Test Bit Name Description This register is used to place the BMU/BIU into various test mode to support Test/Debug. This register is writable only when the ENTST bit in CSR4 and the STOP bit of CSR0 are both set. The functions controlled by this register are enabled only if the ENTST bit is set. ENTST should be set before anything in CSR124 can be programmed, including RUNTACC. ENTST must be reset after writing to CSR124 before writing to any other register. If it is done, the PCnet-32 controller will not run. All bits in this register or cleared by H_RESET or S_RESET and are not affected by STOP. 31-16 RES Reserved locations. Written zeros and read as undefined. Reserved locations. written as zero. Read as and
Receive Collision Count. Indicates th e t o ta l nu m b e r o f c o l l i s i on s encountered by the receiver since the last reset of the counter. RCC will roll over to a count of zero fr om the value 65535. The RCVCCO bit of CSR4 (bit 5) will be set each time that this occurs. The RCC value is read accessible at all times, regardless of the value of the STOP bit. Write operations are ignored. RCC is cleared by H _ R E S E T o r S _ R E S E T o r by setting the STOP bit. A write to this register performs an increment when the ENTST bit in CSR4 is set.
CSR122: Receive Frame Alignment Control Bit Name Description Reserved locations. Written zeros and read as undefined. as 15-5 4 RES GPSIEN 31-16 RES 15-1 0 RES
Reserved locations, written as zeros and read as undefined.
RCVALGN Receive Frame Align. When set, this bit forces the data field of ISO 8802-3 (IEEE/ANSI 802.3) frames to align to 0 MOD 4 address boundaries (i.e. double word aligned addresses). It is important to note that this feature will only function c o r r e c t l y i f a l l r e c e i v e b u f fe r boundaries are double-word aligned and all receive buffers have 0 MOD 4 lengths. In order to accomplish the da ta a li g nm en t, th e P C ne t- 3 2 controller simply inserts two bytes of random data at the beginning of the receive packet (i.e. before the ISO 8802-3 (IEEE/ ANSI 802.3) destination address field). The MCNT field reported to the receive descriptor will not include the extra two bytes. RCVALGN is cleared by H_RESET or S_RESET and is not affected by STOP. Read/write accessible only when STOP bit is set.
This bit places the PCnet-32 controller in the GPSI mode. This mode will reconfigure the System Interface Address Pins so that the GPSI port is exposed. This allows bypassing the MENDEC T-MAU logic. The GPSI mode may also be enabled by test shadow bits setting of BCR18, bits 4 and 3 as in Table 44. See Table 45 for pin reconfiguration in GPSI mode. Note that when the GPSI mode is invoked, only the lower 24 bits of the address bus are available. During Software Relocatable Mode the LED2 pin must be pulled LOW. IOAW24 (BCR21[8]) must be set to allow slave operations. Dur ing master accesses in GPSI mode, the PCnet-32 controller will not drive the upper 8 bits of the address bus with address information.
3
RPA
Runt Packet Accept. This bit forces the receive logic to accept runt packets (packets shorter than 64 bytes). The state of the RPA bit can be changed only when the device is
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in the test mode (when the ENTST bit in CSR4 is set to ONE). To enable RPA, software must first write a ONE to the ENTST bit. Next, software must write a ONE to the RPA bit. Finally, software must write a ZERO to the ENTST bit to take the device out of test mode operation. Once the
RPA bit has been set to ONE, the device will remain in the Runt Packet Accept mode until the RPA bit is cleared to ZERO. 2-0 RES Reserved locations. Written zeros and read as undefined. as
Table 44. GPSI Mode Selection
TSTSHDW Value (BCR18[4:3]) 00 PVALID (BCR19[15]) X GPSIEN Operating Mode Normal Operating Mode GPSI Mode Reserved Reserved Normal Operating Mode GPSI Mode
0
10 01 11 XX
1 1 1 0
X 0 X 0
XX
0
1
Table 45. GPSI Pin Configurations
GPSI Function GPSI I/O Type O O I I I I I LANCE GPSI Pin TX TENA TCLK CLSN RENA RCLK RX ILACC GPSI Pin TXD RTS TXC CDT CRS RXC RXD PCnet-32/ PCnet-ISA GPSI Pin TXDAT TXEN STDCLK CLSN RXCRS SRDCLK RXDAT PCnet-32 Pin Number 132 133 134 137 138 140 141 PCnet-32 Normal Pin Function A31 A30 A29 A28 A27 A26 A25
Transmit Data Transmit Enable Transmit Clock Collision Receive Carrier Sense Receive Clock Receive Data
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Bus Configuration Registers
The Bus Configuration Registers (BCR) are used to program the configuration of the bus interface and other special features of the PCnet-32 controller that are not related to the IEEE 8802-3 MAC functions. The BCRs are accessed by first setting the appropriate RAP value, and then by performing a slave access to the BDP. All BCR registers are 16 bits in width in WIO mode and 32 bits in width in DWIO mode. The upper 16 bits of all BCR registers is undefined when in DWIO mode. These bits should be written as ZEROs and should be treated as undefined when read. The "Default" value given for any BCR is the value in the register after H_RESET, and is hexadecimal unless otherwise
stated. BCR register values are unaffected by S_RESET and are unaffected by the assertion of the STOP bit. Note that several registers have no default value. BCR3 and BCR8-BCR15 are reserved and have undefined values. BCR2, BCR16, BCR17 and BCR21 are not observable without first being programmed, either through the EEPROM read operation or through the Software Relocatable Mode. Therefore, the only observable values for these registers are those that have been programmed and a default value is not applicable. See Table 46. Writes to those registers marked as "Reserved" will have no effect. Reads from these locations will produce undefined values.
Table 46. Bus Configuration Registers
RAP Addr. Mnemonic Default (Hex) Name User 1 2 3 4 5 6 7 8-15 16 17 18 19 20 21 MSWRA MC Reserved LNKST LED1 LED2 LED3 Reserved IOBASEL IOBASEU BSBC EECAS SWSTYLE INTCON 0005 N/A* N/A 00C0 0084 0088 0090 N/A N/A* N/A* 2101 0002 0000 N/A* I/O Base Address Lower I/O Base Address Upper Burst Size and Bus Control EEPROM Control and Status Software Style Interrupt Control Link Status (Default) Receive (Default) Receive Polarity (Default) Transmit (Default) Master Mode Write Active Miscellaneous Configuration No Yes No Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Programmability EEPROM No Yes No No No No No No Yes Yes Yes No No Yes SRM No Yes No No No No No No Yes Yes No No No Yes
Key: SRM = Software Relocatable Mode * Registers marked with an asterisk (*) have no default value, since they are not observable without first being programmed, either through the EEPROM read operation or through the Software Relocatable Mode. Therefore, the only observable values for these registers are those that have been programmed and a default value is not applicable.
BCR0: Master Mode Read Active Bit 31-16 15-0 Name RES MSRDA Description Reserved locations. Written zeros and read as undefined. as
Writes to this register have no effect on the operation of the PCnet-32 controller and will not alter the value that is read. BCR1: Master Mode Write Active Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES
Reserved locations. After H_RESET, the value in this register will be 0005. The settings of this register will have no effect on any PCnet-32 controller function.
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15-0
MSWRA
Reserved locations. After H_RESET, the value in this register will be 0005. The settings of this register will have no effect on any PCnet-32 controller function. Writes to this register have no effect on the operation of the PCnet-32 controller and will not alter the value that is read.
7
INTLEVEL Interrupt Level. This bit allows the i n te r r u p t o u tp u t s i g n a l s to b e programmed for edge or levelsensitive applications. When INTLEVEL is set to a ZERO, the selected interrupt pin is c o n f i g u r e d fo r e d g e s e n s i t i ve operation. In this mode, an interrupt request is signaled by a high level driven on the selected interrupt pin by the PCnet-32 controller. When the interrupt is cleared, the selected interrupt pin is driven to a low level by the PCnet-32 controller. This mode is intended for systems that do not allow interrupt channels to be shared by multiple devices. When INTLEVEL is set to a ONE, the selected interrupt pin is c o n f i g u r e d fo r l eve l s e n s i t i ve operation. In this mode, an interrupt request is signaled by a low level driven on the selected interrupt pin by the PCnet-32 controller. When the interrupt is cleared, the selected i nt er r up t p i n i s f l oa te d by th e PCnet-32 controller and allowed to be pulled to a high level by an external pull-up device. This mode is intended for systems which allow the interrupt signal to be shared by multiple devices. This bit is reset to ZERO by H_RESET and is unaffected by R_RESET or STOP.
BCR2: Miscellaneous Configuration Bit Name Description Note that all bits in this register are programmable through the EEPROM PREAD operation and through the Software Relocatable Mode operation. 31-16 RES 15 RES Reserved locations. Written zeros and read as undefined. as
Reserved location. Written and read as zero.
14 T-MAULOOP When set, this bit allows external loopback packets to pass onto the n e t w o r k t h r o u g h t h e T- M AU interface, if the T-MAU interface has b e e n s e l e c t e d . I f t h e T- M AU interface has not been selected, then this bit has no effect. This bit is reset to ZERO by H_RESET and is unaffected by S_RESET or STOP. 13-9 8 RES Reserved locations. Written and read as zero. 6-4 3 RES
IESRWE IEEE Shadow Ram Write Enable. The PCnet-32 controller contains a shadow RAM on board for storage of the IEEE address following the serial EEPROM read operation. Accesses to APROM I/O Resources will be directed toward this RAM. When IESRWE is set to a ONE, then 32-bit and 16-bit write access to the shadow RAM will be enabled. When IESRWE is set to a ZERO, then 32-bit and 16-bit write access to the shadow RAM will be disabled. At no time are 8-bit write accesses to the shadow RAM allowed. This bit is reset to ZERO by H_RESET and is unaffected by S_RESET or STOP.
Reserved locations. Written and read as zero.
EADISEL EADI Select. When set, this bit configures three of the four LED outputs to function as the outputs of an EADI interface. LED1 becomes SFBD, LED2 becomes SRDCLK an d L ED PRE 3 be co me s S RD. LNKST continues to function as an LED output. In addition to these reassignments, the INTR2 pin will be reassigned to function as the EAR pin. This bit is reset to ZERO by H_RESET and is unaffected by S_RESET or STOP.
2
AWAKE
Auto-Wake. If LNKST is set and AWAKE = "1", the 10BASE-T receive circuitry is active during sleep
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and listens for Link Pulses. LNKST indicates Link Status and goes active if the 10BASE-T port comes of out of "link fail" state. This LNKST pin can be used by external circuitry to re-enable the PCnet-32 controller and/or other devices. When AWAKE = "0", the Auto-Wake circuitry is disabled. This bit only has m e a n i n g wh e n t h e 1 0 B A S E - T network interface is selected. This bit is reset to ZERO by H_RESET and is unaffected by S_RESET or STOP. 1 ASEL Auto Select. When set, the P Cne t- 32 c on tr ol l er wi l l a ut omatically select the operating media interface port, unless the user has selected GPSI mode through appropriate programming of the PORTSEL bits of the Mode Register (CSR15). If GPSI mode has not been selected and ASEL has been set to a ONE, then when the 10BASE-T transceiver is in the link pass state (due to receiving valid frame data and/or Link Test pulses or the DLNKTST bit is set), the 10BASE-T port will be used. If GPSI mode has not been selected and ASEL has been set to a ONE, then when the 10BASE-T port is port will be used. Switching between the por ts will not occur during transmission, to avoid any type of fragment generation. When ASEL is set to ONE, Link Beat Pulses will be transmitted on the 10BASE-T port, regardless of the state of Link Status. When ASEL is reset to ZERO, Link Beat Pulses will only be transmitted on the 10BASE-T port when the PORTSEL bits of the Mode Register (CSR15) have selected 10BASE-T as the active port. When ASEL is set to a ZERO, then the selected network port will be determined by the settings of the PORTSEL bits of CSR15. The ASEL bit is reset to ONE by H_RESET and is unaffected by S_RESET or STOP.
The network port configuration are as follows:
PORTSEL(1:0) 0X 0X 00 01 10 11
ASEL (BCR2[1]) 1 1 0 0 X X
Link Status (of 10BASE-T) 0 1 X X X X
Network Port AUI 10BASE-T AUI 10BASE-T GPSI Reserved
0
RES
Reserved location. The default value of this bit is a ZERO. Writing a ONE to this bit has no effect on device function. Existing drivers may write a ONE to this bit, but new drivers should write a ZERO to this bit. Description BCR4 controls the function(s) that the LNKST pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of the enabled functions. BCR4 defaults to Link Status (LNKST) with pulse stretcher enabled (PSE = 1) and is fully programmable. The default setting after H_RESET for the LNKST register is 00C0h. T h e L N K S T r e g i s t e r va l u e i s unaffected by S_RESET or STOP.
BCR4: Link Status LED Bit Name
31-16 RES 15
Reserved locations. Written zeros and read as undefined.
as
LEDOUT This bit indicates the current (nonstretched) value of the LED output pin. A value of ONE in this bit indicates that the OR of the enabled signals is true. The logical value of the LEDOUT status signal is determined by the settings of the individual Status Enable bits of the LED register (Bits 6-0). This bit is READ only by the host, and is unaffected by H_RESET or S_RESET or STOP. This bit is valid only if the network link status is PASS.
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LEDPOL LED Polarity. When this bit has the value ZERO, then the LED pin will be driven to a LOW level whenever the OR of the enabled signals is true and the LED pin will be floated and allowed to float high whenever the OR of the enabled signals is false (i.e. the LED output will be an Open Drain output and the output value will be the inverse of the LEDOUT status bit). When this bit has the value ONE, then the LED pin will be driven to a HIGH level whenever the OR of the enabled signals is true and the LED pin will be driven to a LOW level whenever the OR of the enabled signals is false (i.e. the LED output will be a Totem Pole output and the outp ut va lue wi ll be the s am e polarity as the LEDOUT status bit). The setting of this bit will not affect the polarity of the LEDOUT bit for this register.
network that has passed the address match function for this node. All address matching modes are included: Physical, Logical filtering, Promiscuous, Broadcast, and EADI. A value of 0 disables the signal. A value of 1 enables the signal. 4 XMTE Transmit status Enable. Indicates PCnet-32 controller transmit activity. A value of 0 disables the signal. A value of 1 enables the signal. 3 RXPOLE Receive Polarity status Enable. In di c at es th e c u r r en t Re c ei ve Polarity condition on the Twisted Pair interface. A value of ONE indicates that the polarity of the RXD pair has been reversed. A value of ZERO indicates that the polarity of the RXD pair has not been reversed. Receive polarity indication is valid only if the LNKST bit of BCR4 indicates link PASS status. A value of 0 disables the signal. A value of 1 enables the signal. 2 RCVE Receive status Enable. Indicates receive activity on the network. A value of 0 disables the signal. A value of 1 enables the signal. 1 JABE Jabber status Enable. Indicates that the PCnet-32 controller is jabbering on the network. A value of 0 disables the signal. A value of 1 enables the signal. 0 COLE Collision status Enable. Indicates collision activity on the network. When the AUI por t is selected, collision activity during the 4.0 ms i n t e r n a l fo l l o w i n g a t r a n s m i t completion (SQE internal) will not activate the LEDOUT bit. A value of 0 disables the signal. A value of 1 enables the signal. BCR5: LED1 Status Bit Name Description BCR5 controls the function(s) that the LED1 pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of
13
LEDDIS
LED Disable. This bit is used to disable the LED output. When LEDDIS has the value ONE, then the LED output will always be floated. When LEDDIS has the value ZERO, then the LED output va lu e wi ll be g ove r ned by th e LEDOUT and LEDPOL values. Reserved locations. Written ZEROs, read as undefined. as
12-8 7
RES PSE
Pulse Stretcher Enable. Extends the LED illumination time for each new occurrence of the enabled function for this LED output. A value of 0 disables the function. A value of 1 enables the function.
6
LNKSTE Link Status Enable. Indicates the current link status on the Twisted Pair interface. When this bit is set, a value of ONE will be passed to the LEDOUT signal to indicate that the link status state is PASS. A value of ZERO will be passed to the LEDOUT signal to indicate that the link status state is FAIL. A value of 0 disables the signal. A value of 1 enables the signal.
5
RCVME
Receive Match status Enable. Indicates receive activity on the
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the enabled functions. BCR5 defaults to Receive Status (RCV) with pulse stretcher enabled (PSE = 1) and is fully programmable. The default setting after H_RESET for the LED1 register is 0084h. The LED1 register value is unaffected by S_RESET or STOP. 31-16 RES 15 Reserved locations. Written zeros and read as undefined. as 12-8 7 RES PSE
the LED output will always be floated. When LEDDIS has the value ZERO, then the LED output va lu e wi ll be g over ned by th e LEDOUT and LEDPOL values. Reserved locations. Write ZEROs, read as undefined. as
LEDOUT This bit indicates the current (nonstretched) value of the LED output pin. A value of ONE in this bit indicates that the OR of the enabled signals is true. The logical value of the LEDOUT status signal is determined by the settings of the individual Status Enable bits of the LED register (Bits 6-0). This bit is READ only by the host, and is unaffected by H_RESET S_RESET or STOP. This bit is valid only if the network link status is PASS.
Pulse Stretcher Enable. Extends the LED illumination time for each new occurrence of the enabled function for this LED output. A value of 0 disables the function. A value of 1 enables the function.
6
LNKSTE Link Status Enable. Indicates the current link status on the Twisted Pair interface. When this bit is set, a value of ONE will be passed to the LEDOUT signal to indicate that the link status state is PASS. A value of ZERO will be passed to the LEDOUT signal to indicate that the link status state is FAIL. A value of 0 disables the signal. A value of 1 enables the signal.
5
RCVME
14
LEDPOL LED Polarity. When this bit has the value ZERO, then the LED pin will be driven to a LOW level whenever the OR of the enabled signals is true and the LED pin will be floated and allowed to float high whenever the OR of the enabled signals is false (i.e. the LED output will be an Open Drain output and the output value will be the inverse of the LEDOUT status bit). When this bit has the value ONE, then the LED pin will be driven to a HIGH level whenever the OR of the enabled signals is true and the LED pin will be driven to a LOW level whenever the OR of the enabled signals is false (i.e. the LED output will be a Totem Pole output and the outp ut va lue wi ll be the s am e polarity as the LEDOUT status bit). The setting of this bit will not affect the polarity of the LEDOUT bit for this register.
Receive Match status Enable. Indicates receive activity on the network that has passed the address match function for this node. All address matching modes are included: Physical, Logical filtering, Promiscuous, Broadcast, and EADI. A value of 0 disables the signal. A value of 1 enables the signal.
4
XMTE
Transmit status Enable. Indicates PCnet-32 controller transmit activity. A value of 0 disables the signal. A value of 1 enables the signal.
3
RXPOLE Receive Polarity status E n a bl e. I n d i c a t e s t h e c u r r e n t Receive Polarity condition on the Twisted Pair interface. A value of ONE indicates that the polarity of the RXD pair has been reversed. A value of ZERO indicates that the polarity of the RXD pair has not been reversed. Receive polarity indication is valid only if the LNKST bit of BCR4 indicates link PASS status. A value of 0 disables the signal. A value of 1 enables the signal.
13
LEDDIS
LED Disable. This bit is used to disable the LED output. When LEDDIS has the value ONE, then
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2
RCVE
Receive status Enable. Indicates receive activity on the network. A value of 0 disables the signal. A value of 1 enables the signal.
14
1
JABE
Jabber status Enable. Indicates that the PCnet-32 controller is jabbering on the network. A value of 0 disables the signal. A value of 1 enables the signal.
LEDPOL LED Polarity. When this bit has the value ZERO, then the LED pin will be driven to a LOW level whenever the OR of the enabled signals is true and the LED pin will be floated and allowed to float high whenever the OR of the enabled signals is false (i.e. the LED output will be an Open Drain output and the output value will be the inverse of the LEDOUT status bit). When this bit has the value ONE, then the LED pin will be driven to a HIGH level whenever the OR of the enabled signals is true and the LED pin will be driven to a LOW level whenever the OR of the enabled signals is false (i.e. the LED output will be a Totem Pole output and the outp ut va lue w ill be the s am e polarity as the LEDOUT status bit). The setting of this bit will not affect the polarity of the LEDOUT bit for this register.
0
COLE
Collision status Enable. Indicates collision activity on the network. When the AUI por t is selected, collision activity during the 4.0 ms i n t e r n a l fo l l o w i n g a t r a n s m i t completion (SQE internal) will not activate the LEDOUT bit. A value of 0 disables the signal. A value of 1 enables the signal.
BCR6: LED2 Status Bit Name Description BCR6 controls the function(s) that the LED2 pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of the enabled functions. BCR6 d e fa u l t s t o t w i s t e d p a i r M AU Receive Polarity (RCVPOL) with pulse stretcher enabled (PSE = 1) and is fully programmable. The default setting after H_RESET for the LED2 register is 0088h. The LED2 register value is unaffected by S_RESET or STOP. 31-16 15 RES Reserved locations. Written zeros and read as undefined. as
13
LEDDIS
LED Disable. This bit is used to disable the LED output. When LEDDIS has the value ONE, then the LED output will always be floated. When LEDDIS has the value ZERO, then the LED output va lu e wi ll be g over ned by th e LEDOUT and LEDPOL values. Reserved locations. Write ZEROs, read as undefined. as
12-8 7
RES PSE
Pulse Stretcher Enable. Extends the LED illumination time for each new occurrence of the enabled function for this LED output. A value of 0 disables the function. A value of 1 enables the function.
LEDOUT This bit indicates the current (nonstretched) value of the LED output pin. A value of ONE in this bit indicates that the OR of the enabled signals is true. The logical value of the LEDOUT status signal is determined by the settings of the individual Status Enable bits of the LED register (Bits 11-8 and 5-0). This bit is READ only by the host, and is unaffected by H_RESET S_RESET or STOP. This bit is valid only if the network link status is PASS.
6
LNKSTE Link Status Enable. Indicates the current link status on the Twisted Pair interface. When this bit is set, a value of ONE will be passed to the LEDOUT signal to indicate that the link status state is PASS. A value of ZERO will be passed to the LEDOUT signal to indicate that the link status state is FAIL. A value of 0 disables the signal. A value of 1 enables the signal.
5
RCVME
Receive Match status Enable. Indicates receive activity on the
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network that has passed the address match function for this node. All address matching modes are included: Physical, Logical filtering, Promiscuous, Broadcast, and EADI. A value of 0 disables the signal. A value of 1 enables the signal. 4 XMTE Transmit status Enable. Indicates PCnet-32 controller transmit activity. A value of 0 disables the signal. A value of 1 enables the signal. 3 RXPOLE Receive Polarity status Enable. In di c ate s th e c u r r en t Re c ei ve Polarity condition on the Twisted Pair interface. A value of ONE indicates that the polarity of the RXD pair has been reversed. A value of ZERO indicates that the polarity of the RXD pair has not been reversed. Receive polarity indication is valid only if the LNKST bit of BCR4 indicates link PASS status. A value of 0 disables the signal. A value of 1 enables the signal. 2 RCVE Receive status Enable. Indicates receive activity on the network. A value of 0 disables the signal. A value of 1 enables the signal. 1 JABE Jabber status Enable. Indicates that the PCnet-32 controller is jabbering on the network. A value of 0 disables the signal. A value of 1 enables the signal. 0 COLE Collision status Enable. Indicates collision activity on the network. When the AUI por t is selected, collision activity during the 4.0 ms i n t e r n a l fo l l o w i n g a t r a n s m i t completion (SQE internal) will not activate the LEDOUT bit. A value of 0 disables the signal. A value of 1 enables the signal. BCR7: LED3 Status Bit Name Description BCR7 controls the function(s) that the LEDPRE3 pin displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of 13 LEDDIS 14 31-16 RES 15
the enabled functions. BCR7 defaults to Transmit Status (XMT) with pulse stretcher enabled (PSE = 1) and is fully programmable. The default setting after H_RESET for the LED3 register is 0090h. The LED3 register value is unaffected by S_RESET or STOP. Reserved locations. Written zeros and read as undefined. as
LEDOUT This bit indicates the current (nonstretched) value of the LED output pin. A value of ONE in this bit indicates that the OR of the enabled signals is true. The logical value of the LEDOUT status signal is determined by the settings of the individual Status Enable bits of the LED register (Bits 11-8 and 5-0). This bit is READ only by the host, and is unaffected by H_RESET S_RESET or STOP. This bit is valid only if the network link status is PASS. LEDPOL LED Polarity. When this bit has the value ZERO, then the LED pin will be driven to a LOW level whenever the OR of the enabled signals is true and the LED pin will be floated and allowed to float high whenever the OR of the enabled signals is false (i.e. the LED output will be an Open Drain output and the output value will be the inverse of the LEDOUT status bit). When this bit has the value ONE, then the LED pin will be driven to a HIGH level whenever the OR of the enabled signals is true and the LED pin will be driven to a LOW level whenever the OR of the enabled signals is false (i.e. the LED output will be a Totem Pole output and the outp ut va lue w ill be the s am e polarity as the LEDOUT status bit). The setting of this bit will not affect the polarity of the LEDOUT bit for this register. LED Disable. This bit is used to disable the LED output. When LEDDIS has the value ONE, then the LED output will always be
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floated. When LEDDIS has the value ZERO, then the LED output va lu e wi ll be g ove r ned by th e LEDOUT and LEDPOL values. 12-8 7 RES PSE Reserved locations. Write ZEROs, read as undefined. as
2
RCVE
Receive status Enable. Indicates receive activity on the network. A value of 0 disables the signal. A value of 1 enables the signal.
1
JABE
Pulse Stretcher Enable. Extends the LED illumination time for each new occurrence of the enabled function for this LED output. A value of 0 disables the function. A value of 1 enables the function. 0 COLE
Jabber status Enable. Indicates that the PCnet-32 controller is jabbering on the network. A value of 0 disables the signal. A value of 1 enables the signal. Collision status Enable. Indicates collision activity on the network. When the AUI por t is selected, collision activity during the 4.0 ms i n t e r n a l fo l l o w i n g a t r a n s m i t completion (SQE internal) will not activate the LEDOUT bit. A value of 0 disables the signal. A value of 1 enables the signal.
6
LNKSTE Link Status Enable. Indicates the current link status on the Twisted Pair interface. When this bit is set, a value of ONE will be passed to the LEDOUT signal to indicate that the link status state is PASS. A value of ZERO will be passed to the LEDOUT signal to indicate that the link status state is FAIL. A value of 0 disables the signal. A value of 1 enables the signal.
BCR16: I/O Base Address Lower Bit Name Description Note that all bits in this register are programmable through the EEPROM PREAD operation and through the Software Relocatable Mode operation. 31-16 RES 15-5 Reserved locations. Written zeros and read as undefined. as
5
RCVME
Receive Match status Enable. Indicates receive activity on the network that has passed the address match function for this node. All address matching modes are included: Physical, Logical filtering, Promiscuous, Broadcast, and EADI. A value of 0 disables the signal. A value of 1 enables the signal.
4
XMTE
Transmit status Enable. Indicates PCnet-32 controller transmit activity. A value of 0 disables the signal. A value of 1 enables the signal.
3
RXPOLE Receive Polarity status Enable. In di c ate s th e c u r r en t Re c ei ve Polarity condition on the Twisted Pair interface. A value of ONE indicates that the polarity of the RXD pair has been reversed. A value of ZERO indicates that the polarity of the RXD pair has not been reversed. Receive polarity indication is valid only if the LNKST bit of BCR4 indicates link PASS status. A value of 0 disables the signal. A value of 1 enables the signal.
IOBASEL I/O Base Address Lower 16 bits. These bits are used to determine the location of the PCnet-32 controller in all of I/O space. They function as bits 15 through 5 of the I/ O address of the PCnet-32 controller. Note that the lowest five bits of the PCnet-32 controller I/O space are not programmable. These bits are assumed to be ZEROs. This means that it is not possible to locate the PCnet-32 controller on a space that does not begin on a 32byte block boundary. The value of IOBASEL is determined in either of two ways: 1.The ISOBASEL value may be set during the EEPROM read. 2.If no EEPROM exists, or if there is an error detected in the EEPROM data, then the PCnet-32 controller will enter Software Relocatable Mode, and a specific sequence of write accesses to I/O address 378h will cause the
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IOBASEL value to be updated. Refer to the Software Relocatable Mode section of this document for more details. A direct write access to the I/O Base Address Lower register may be performed. IOBASEL is not S_RESET or STOP. 4-0 RES affected by
BCR18: Burst Size and Bus Control Bit Name Description Note that all bits in this register are programmable through the EEPROM PREAD operation. 31-16 RES 15-11 CLL Reserved locations. Written zeros and read as undefined. as
Reserved locations. Written ZEROs, read as undefined. Description
as
BCR17: I/O Base Address Upper Bit Name Note that all bits in this register are programmable through the EEPROM PREAD operation and software relocatable mode. 31-16 RES 15-0 Reserved locations. Written zeros and read as undefined. as
IOBASEU I/O Base Address Upper 16 bits. These bits are used to determine the location of the PCnet-32 controller in all of I/O space. They function as bits 31 through 16 of the I/O address of the PCnet-32 controller. The value of IOBASEU is determined in either of two ways: 1. The IOBASEU value may be set during the EEPROM read. 2. If no EEPROM exists, or if there is an error detected in the EEPROM data, then the PCnet-32 controller will enter Software Relocatable Mode, and a specific sequence of write accesses to I/O address 378h will cause the IOBASEU value to be updated. Refer to the S o f t wa r e R e l o c a t a bl e M o d e section of this document for more details. A direct write access to the I/O Base Address Upper register may be performed. IOBASEU is not S_RESET or STOP. affected by
Cache Line Length. These bits are used to deter mine how often a cache invalidation cycle needs to be performed when Generate Cache I nva l i d a t i o n C y c l e s h a s b e e n activated by setting the GCIC bit (bit 10 of BCR18) to a one. CLL values are interpreted as multiples of 4 bytes. For example, a CLL value of 00001b means the cache line length is 4 bytes and a cache invalidation cycle (assertion of EADS) will be performed every 4 bytes. A CLL value of 00010b means the cache line length is 8 bytes, and a cache invalidation cycle will be performed every 8 bytes. A CLL value of 00100 means the cache line length is 16 bytes. A value of 00000 means that the cache line size is "infinite". In other words, a single EADS assertion will be performed on the first access at the beginning of each bu s m a s t e r s h i p p e r i o d ( w r i t e accesses only) and no subsequent EADS asser tions will be made during this bus mastership period. Cache invalidation cycles are performed only during PCnet-32 controller bus master write accesses. Some CLL values are reserved (see chart below). The portion of the Address Bus that will be floated at the time of an address hold operation (AHOLD asserted) will be determined by the value of the Cache Line Length register. The following chart lists all of the legal values of CLL showing the portion of the Address Bus that wil l bec ome floa ted dur ing a n address hold operation:
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CLL Value 00000 00001 00010 00011 00100 00101-00111 01000 01001 -01111 10000 10001- 11111
Portion of Address Bus Floated During AHOLD None A31-A2 A31-A3 Reserved CLL Value A31-A4 Reserved CLL Values A31-A5 Reserved CLL Values A31-A6 Reserved CLL Values
according to the GCIC and CLL bits, regardless of the setting of the Am486/Am386 pin. IWBACK Ignore WBACK signal. When this bit is set and the VESA VL-Bus Mode has been selected, then the PCnet-32 device will operate as though the WBACK input pin is always held HIGH, even though the real value of the WBACK input may change. This function is provided to a l l ow t h e P C n e t - 3 2 d ev i c e t o operate in systems which violate VESA VL-Bus WBACK operation by either floating this pin or by always driving this pin LOW. LEADS is always asserted with each assertion of ADS when VESA VLBus mode has been s elec ted, regardless of the setting of the GCIC/IWBACK bit. GCIC/IWBACK is cleared by H_RESET and is not affected by S_RESET or STOP. 9 PRPCNET Priority PCnet. This bit is used to set the pr ior ity of the dai sy chai n arbitration logic that resides within the PCnet-32 controller. When PRPCNET = 1, the priority of the daisy chain logic is set to PCnet-32 controller highest priority, External d ev i c e l o w e s t p r i o r i t y. W h e n PRPCNET = 0, the priority of the daisy chain logic is set to External device highest priority, PCnet-32 controller lowest priority. In the case PRPCNET = 0, where the PCnet-32 controller has lower priority than the external device and the PCnet-32 controller is preempted due to a HOLDI request from the external device, the PCnet-32 controller will complete the current sequence of accesses and then pass the HLDA to the external device by asserting the HLDAO signa l. The HO LD output signal from the PCnet-32 controller will not change state during the HLDAO hand-off. If the PCnet-32 controller is performing a linear burst, then the PCnet-32 controller will complete the linear burst and then pass the HLDA to the external device through the HLDAO signal. For more details on exact timing of preemption events, see the
Note that the default value of CLL after RESET is 00100b. All timing diagrams in this document are drawn with the assumption that this is the value of CLL. When VESA VL-Bus mode is sel ecte d, then the LEA DS pi n functions as if CLL = 00001b regardless of the actual CLL setting. CLL is set to 00100b by H_RESET and is not affected by S_RESET or STOP. 10 GCIC/IWBACKGenerate Cache Invalidation Cycles. Ignore WBACK signal. GCIC Generate Cache Invalidation Cycles. When this bit is set and the Am486 mode has been selected, then the PCnet-32 controller assumes that the host system contains a cache, but the host system does not snoop the local bus master accesses of the PCnet-32 controller, and therefore, that cache invalidation cyc les must be generated by the PCnet-32 controller for PCnet-32 controller master accesses. PCnet-32 controller will not perform snoops to invalidate cache lines for local bus ac c es s es th at oth er l oc al bus masters may have executed. When GCIC is a ZERO, the PCnet-32 controller assumes that logic in the host system will create the cache invalidation cycles that may be necessary as a result of PCnet-32 controller local bus master accesses. The cache invalidation l o g i c p e r fo r m s i t s f u n c t i o n s AM79C965A
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individual descriptions of the various DMA transfers. PRPCNET is cleared by H_RESET and is not affected by S_RESET or STOP. The default setting for this bit will be PRPCNET = 0. This default value reflects the nature of the CPU's handling of a HOLD request (i.e. the CPU has lowest priority). By making this the default setting, the PCnet-32 controller response to HOLDI is as close as possible to the timing of the CPU response to HOLD, so that minimal design difficulty will be created by inserting the PCnet-32 controller into the system as the mediating device between the CPU and the extension bus chipset. 8 RES Reserved bit. Must be written as a ONE. Will be read as a ONE. This reserved location is SET by H_RESET and is not affected by S_RESET or STOP. 7 DWIO Double Word I/O. When set, this bit indicates that the PCnet-32 controller is programmed for DWIO m o d e. W h e n c l e a r e d , t h i s b i t indicates that the PCnet-32 controller is programmed for Word I/O mode. This bit affects the I/O Resource Offset map and it affects the defined width of the PCnet-32 controller's I/O resources. See the DWIO and WIO sections for more details. The PCnet-32 controller will set DWIO if it detects a double-word write access to offset 10h from the PCnet-32 controller I/O Base Address (corresponding to the RDP resource). A double word write access to offset 10h is the only way that the DWIO bit can be set. DWIO cannot be set by a direct write to BCR18. Once the DWIO bit has been set to a ONE, only a H_RESET can reset it to a ZERO. DWIO is read only by the host. DWIO is cleared by H_RESET and is not affected by S_RESET or STOP.
6
BREADE Burst Read Enable. When set, this bit enables Linear Bursting during memor y read accesses, where Linear Bursting is defined to mean that only the first transfer in the current bus arbitration will contain an address cycle. Subsequent transfers will consist of data only. However, the entire address bus will still be driven with appropr iate val ues d ur i ng t he s u bs eq uen t cycles, but ADS will not be asserted. When cleared, this bit prevents the part from performing linear bursting during read accesses. In no case will the par t linearly burst a descriptor access or an initialization access. BREADE is cleared by H_RESET and is not affected by S_RESET or STOP. Burst Read activity is not allowed when the BCLK frequency is >33 MHz. Linear bursting is disabled in VL-Bus systems that operate above this frequency by connecting the VLBEN pin to either ID(3) (for VLBus version 1.0 systems) or ID(4) AND ID(3) AND ID(1) AND ID(0) (for VL-Bus version 1.1 or 2.0 systems). In Am486-style systems that have BCLK frequencies above 33 MHz, disabling the linear burst capability is ideally carried out through EEPROM bit programming, since the EEPROM programming can be setup for a par ticular machine's architecture. When the VLBEN pin has been reset to a ZERO, then the BREADE bit will be forced to a value of ZERO. Any attempt to change this value by writing to the BREADE bit location will have no effect.
5
BWRITE Burst Write Enable. When set, this bit enables Linear Bursting during memor y write accesses, where Linear Bursting is defined to mean that only the first transfer in the current bus arbitration will contain an address cycle. Subsequent transfers will consist of data only. However, the entire address bus will still be driven with appropr iate val ues d ur i ng t he s u bs eq uen t cycles, but ADS will not be asserted. When cleared, this bit prevents the
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part from performing linear bursting during write accesses. In no case will the par t linearly burst a descriptor access or an initialization access. BWRITE is cleared by H_RESET and is not affected by S_RESET or STOP. Burst Write activity is not allowed when the BCLK frequency is >33 MHz. Linear bursting is disabled in VL-Bus systems that operate above this frequency by connecting the VLBEN pin to either ID(3) (for VLBus version 1.0 systems) or ID(4) AND ID(3) AND ID(1) AND ID(0) (for VL-Bus version 1.1 or 2.0 systems). In Am486-style systems that have BCLK frequencies above 33 MHz, disabling the linear burst capability is ideally carried out through EEPROM bit programming, since the EEPROM programming can be setup for a par ticular machine's architecture. When the VLBEN pin has been reset to a ZERO, then the BWRITE bit will be forced to a value of ZERO. Any attempt to change this value by writing to the BWRITE bit location will have no effect. 4-3 TSTSHDW Test Shadow bits. These bits are used to place the PCnet-32 controller into GPSI mode. BCR18[3] must be set to ZERO. The ope ratin g mo des pos s ible ar e indicated in Table 47. See Table 48 for pin reconfiguration in GPSI mode.
Note that when the GPSI mode is invoked, only the lower 24 bits of the address bus are available. IOAW24 (BCR21[8]) must be set to allow slave operations. During master accesses in GPSI mode, the PCnet-32 controller will not drive the upper 8 bits of the address bus with address information. These bits are not writable, regardless of the setting of the ENTST bit in CSR4. Values may only be programmed to these bits through the EEPROM read operation. BCR18[4:3] are set to 0 by H_RESET and are unaffected by S_RESET or STOP. 2-0 LINBC[2:0] Linear Burst Count. The 3-bit value in this register sets the upper limit for the number of transfer cycles in a Linear Burst. This limit determines how often the PCnet-32 controller will assert the ADS signal during linear burst transfers. Each time that the inter preted value of LINBC transfers is reached, the PCnet-32 controller will assert the ADS signal with a new valid address. The LINBC value should contain only one active bit. LINBC values with m o r e t ha n on e a c t i ve b i t m ay produce predictable results, but such values will not be compatible with future AMD network controllers. The LINBC entry is shifted by two bits before being used by the PCnet32 controller. For example, the value LINBC[2:0] = 010 is understood by the PCnet-32 con-troller to mean 01000 = 8. Therefore, the value LINBC[2:0] = 010 will cause the PCnet-32 controller to issue a new ADS every 01000b = 8 transfers. T h e P C n e t - 3 2 c o n t r o l l e r m ay linearly burst fewer than the value represented by LINBC, due to other conditions that cause the burst to end prematurely. Therefore, LINBC should be regarded as an upper limit to the length of linear burst.
TSTSHDW Value (BCR18[4:3]) 00
PVALID GPSIEN (BCR19[15]) (CSR124[4]) X 0
Operating Mode Normal Operating Mode GPSI Mode Reserved Reserved Normal Operating Mode GPSI Mode
10 01 11 XX
1 1 1 0
X 0 X 0
XX
0
1
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Table 48. GPSI Pin Configuration
GPSI Function GPSI I/O Type O O I I I I I LANCE GPSI Pin TX TENA TCLK CLSN RENA RCLK RX ILACC GPSI Pin TXD RTS TXC CDT CRS RXC RXD PCnet-32/ PCnet-ISA GPSI Pin TXDAT TXEN STDCLK CLSN RXCRS SRDCLK RXDAT PCnet-32 Pin Number 132 133 134 137 138 140 141 PCnet-32 Normal Pin Function A31 A30 A29 A28 A27 A26 A25
Transmit Data Transmit Enable Transmit Clock Collision Receive Carrier Sense Receive Clock Receive Data
Note that linear burst operation will only begin on certain addresses. The general rule for linear burst starting addresses is: A[31:0] MOD (LINBC x 16) = 0. Table 49 illustrates all possible starting address values for all legal LINBC values (only 1, 2, and 4 are legal; other values are reserved). Note that A[31:8] are don't care values for all addresses. (A[1:0] do not exist within a 32 bit system, however, they are valid bits within the buffer pointer field of descriptor word 0.)
Table 49. Linear Burst Cycles
LINBC[2:0] LBS = Linear Burst Size (No. of Transfers) Size of Burst (Byte) Linear Burst Beginning Addresses (A[31:6] = Don't Care) A[5:0] = 00, 10, 20, 30 00, 20 00
Table 50. Linear Burst Address Bus
LINBC Value 001 010 100 Portion of Address Bus Stable During Linear Burst A[31:4] A[31:5] A[31:6]
1 2 4
4 8 16
16 32 64
The assertion of RDYRTN in the place of BRDY within a linear burst cycle will cause the linear burst to be i n t e r r u p t e d . I n t h a t c a s e, t h e PCnet-32 controller will revert to ordinary two-cycle transfers, except that BLAST will remain de-asserted to show that linear bursting is being requested by the PCnet-32 controller. This situation is defined as interrupted linear burst cycles. If BRDY is sampled as asser ted (without also sampling RDYRTN asserted during the same access) dur ing interr upted linear burst cycles, then linear bursting will resume. There are several events which may cause early termination of linear burst. Among those events are: no more data available for transfer in either a buffer or in the FIFO or if either the Cycle Register (CSR80) or the Bus Activity Timer Register (CSR82) times out. In any of these cases, the PCnet-32 controller will end the Linear Burst by asserting BLAST and then releasing the bus. A Par tial Linear Burst may have been sent out before the assertion of BLAST, where "Partial Linear Burst" refers to the case where the number of data words transferred between the last asser ted ADS and the
Due to the beginning address restrictions just given, it can be shown that some por tion of the address bus will be held stable throughout each linear burst sequence, while the lowest portion of the address bus will change value with each new cycle. The portion of the address bus that will be held stable during a linear burst access is given in Table 50.
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asser tion of BLAST is less than LINBC. The value on the address bus will be updated with appropriate values every clock cycle during linear burst operations, even though ADS will not be asserted during every clock cycle. Certain combinations of watermark programming and LINBC programming may create situations where no linear bursting is possible, o r w h e r e t h e F I F O m ay b e excessively read or excessively written. Such combinations are declared as illegal. Combinations of watermark settings and LINBC settings must obey the following relationship: watermark (in bytes) LINBC (in bytes) Combinations of watermark and LINBC settings that violate this rule may cause unexpected behavior. LINBC is set to the value of 001 by H_RESET and is not affected by S_RESET or STOP. This gives a default linear burst length of 4 transfers = 001 x 4. BCR19: EEPROM Control and Status Bit Name Description Reserved locations. Written zeros and read as undefined. as 31-16 RES 15 PVALID
PVALID is set to ZERO during H_RESET and is unaffected by S _ R E S E T o r t h e S TO P b i t . However, following the H_RESET operation, an automatic read of the EEPROM will be performed. Just as i s t r ue fo r th e no r ma l P RE A D command, at the end of this aut omat ic re ad op erati on, th e PVALID bit may be set to ONE. Therefore, H_RESET will set the PVALID bit to ZERO at first, but the automatic EEPROM read operation may later set PVALID to a ONE. If PVALID becomes ZERO following an EEPROM read operation (either a u to m a ti c al l y g e ne r at e d a f te r H_RESET, or requested through PREAD), then all EEPROMprogrammable BCR locations will be reset to their H_RESET values. If no EEPROM is present at the EESK, EEDI and EEDO pins, then all attempted PREAD commands will terminate early and PVALID will NOT be set. This applies to the automatic read of the EEPROM after H_RESET as well as to hostinitiated PREAD commands. 14 PREAD EEPROM Read command bit. When this bit is set to a ONE by the host, the PVALID bit (BCR19[15]) will immediately be reset to a ZERO and then the PCnet-32 controller will perform a read operation of 36 bytes from the EEPROM through the microwire interface. The EEPROM data that is fetched during the read will be stored in the appropriate inter nal registers on board the P C n e t - 3 2 c o n t r o l l e r. U p o n completion of the EEPROM read operation, the PCnet-32 controller will assert the PVALID bit. EEPROM contents will be indirectly accessible to the host through I/O read accesses to the Address PROM (offsets 0h through Fh) and through I/O read accesses to other EEPROM programmable registers. Note that I/O read accesses from these locations will not actually access the EEPROM itself, but instead will access the PCnet-32 controller's internal copy of the E E P RO M c o n t e n t s . I / O w r i t e
EEPROM Valid status bit. This bit is read only by the host. A value of ONE in this bit indicates that a PREAD operation has occurred, and that 1) there is an EEPROM connected to the PCnet-32 controller microwire interface pins and 2) the contents read from the EEPROM have passed the checksum verification operation. A value of ZERO in this bit indicates that the contents of the EEPROM are different from the contents of the applicable PCnet-32 controller onboard registers and/or that the checksum for the entire 36 bytes of EEPROM is incorrect or that no E E P RO M i s c o n n e c t e d t o th e microwire interface pins.
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accesses to these locations may change the PCnet-32 controller register contents, but the EEPROM loc ati ons will not be a ffe cted . EEPROM locations may be accessed directly through BCR19. At the end of the read operation, the PREAD bit will automatically be reset to a ZERO by the PCnet-32 controller and PVALID will bet set, provided that an EEPROM existed on the microwire interface pins and that the checksum for the entire 36 bytes of EEPROM was correct. Note that when PREAD is set to a ONE, then the PCnet-32 controller will no longer respond to I/O accesses directed toward it, until the PREAD operation has completed successfully. If a PREAD command is given to the PCnet-32 controller but no EEPROM is attached to the microwire interface pins, then the PREAD command will terminate early, the PREAD bit will be cleared to a ZERO and the PVALID bit will remain reset with a value of ZERO. The PCnet-32 controller will then enter Software Relocatable Mode to await further programming. This applies to the automatic read of the EEPROM after H_RESET as well as to host initiated PREAD commands. EEPROM programmable locations on board the PCnet-32 controller will be set to their default values by such an aborted PREAD operation. For example, if the abor ted PREAD operation immediately followed the H_RESET operation, then the final state of the EEPROM programmable locations will be equal to the H_RESET programming for those locations. If a PREAD command is given to the PCnet-32 controller and the autodetection pin (EESK/LED1/ SFBD) indicates that no EEPROM is present, then the EEPROM read operation will still be attempted.
Note that at the end of the H_RESET operation, a read of the E E P R O M w i l l b e p e r fo r m e d automati cally. This H_RESETgenerated EEPROM read function will not proceed if the auto-detection pin (EESK/LED1/SFBD) indicates that no EEPROM is present. Instead, Software Relocatable Mode will be entered immediately. PREAD is set to ZERO during H_RESET and is unaffected by S_RESET or STOP. PREAD is only writable when the STOP bit is set to ONE. 13 EEDET EEPROM Detect. This bit indicates the sampled value of the EESK/ L E D1 / S FB D p i n a t th e e n d o f H_RESET. The value of this bit is independent whether or not an EEPROM is actually present at the EEPROM interface. It is only a function of the sampled value of the EESK/LEDI/SFBD pin at the end of H_RESET. The value of this bit is determined at the end of the H_RESET operation. It is unaffected by S_RESET or STOP. This bit is not writable. It is read only. Table 51 indicates the possible combinations of EEDET and the existence of an EEPROM and the resulting operations that are possible on the EEPROM microwire interface. 12-5 4 RES EEN Reserved locations. Written ZERO, read as undefined. as
EEPROM port enable. When this bit is set to a one, it causes the values of EBUSY, ECS, ESK and EDI to be driven onto the SHFBUSY, EECS, EESK and EEDI pins, respectively. When this bit is reset to a zero, then the SHFBUSY pin will be driven with the inverse of the PVALID (bit 15 of BCR19) value. PVALID is set to "ONE" if the EEPROM read was successful. It is set to "ZERO" otherwise.
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Table 51. EEDET Effects on EEPROM Operation
EEDET Value (BCR19[3]) 0 EEPROM Connected? No Result if PREAD is set to ONE EEPROM read operation is attempted. Entire read sequence will occur, checksum failure will result, PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum operation will pass, PVALID is set to ONE. EEPROM read operation is attempted. Entire read sequence will occur, checksum failure will result, PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum operation will pass, PVALID is set to ONE. Result of Automatic EEPROM Read Operation Following H_RESET First TWO EESK clock cycles are generated, then EEPROM read operation is aborted and PVALID is reset to ZERO. First TWO EESK clock cycles are generated, then EEPROM read operation is aborted and PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum failure will result, PVALID is reset to ZERO. EEPROM read operation is attempted. Entire read sequence will occur, checksum operation will pass, PVALID is set to ONE.
0
Yes
1
No
1
Yes
If EEN = 0 and no EEPROM read function is currently active, then EECS will be driven LOW. When EEN = 0 and no EEPROM read function is currently active, EESK and EEDI pins will be driven by the LED registers BCR5 and BCR4, respectively. See Table 52. EEN is set to ZERO by H_RESET and is unaffected by S_RESET or STOP. 3 EBUSY EEPROM BUSY. This bit controls the value of the SHFBUSY pin of the PCnet-32 controller when the EEN bit is set to ONE and the PREAD bit is set to ZERO. This bit is used to indicate to exter nal EEPROMprogrammable logic that an EEPROM access is occurring. When user programming of the EEPROM is desired through the BCR19 EEPROM Port, then EBUSY should be set to ONE before EEN is s e t to O NE i n s y s t e m s w h er e EEPROM-programmable external logic exists. At the end of the EEPROM programming operation, EBUSY should either remain set at ONE until after EEN is set to ZERO, or the user may reset EBUSY to ZERO with EEN = 1 immediately following a read of EEPROM byte locations 35 and 36, which should be the last accesses performed
dur ing BCR19 accesses to the EEPROM. A programmed PREAD operation following the BCR19 EEPROM programming accesses will cause the SHFBUSY pin to b e c o m e L OW i f t h e E E P RO M checksum is verified. EBUSY has no effect on the output value of the SHFBUSY pin unless the PREAD bit is set to ZERO and the EEN bit is set to ONE. EBUSY is set to ZERO by H_RESET and is unaffected by S_RESET or STOP. 2 ECS EEPROM Chip Select. This bit is used to control the value of the EECS pin of the microwire interface when the EEN bit is set to ONE and the PREAD bit is set to ZERO. If EEN = "1" and PREAD = "0" and ECS is set to a ONE, then the EECS pin will be forced to a HIGH level at the rising edge of the next BCLK following bit programming. If EEN = "1" and PREAD = "0" and ECS is set to a ZERO, then the EECS pin will be forced to a LOW level at the rising edge of the next BCLK following bit programming. ECS has no effect on the output value of the EECS pin unless the PREAD bit is set to ZERO and the EEN bit is set to ONE.
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ECS is set to ZERO by H_RESET and is unaffected by S_RESET or STOP. 1 ESK EEPROM Serial Clock. This bit and the EDI/EDO bit are used to control host access to the EEPROM. Values programmed to this bit are placed onto the EESK pin at the rising edge of the next BCLK following bit
Table 52. EEPROM Enable
Reset Pin
programming, except when the PREAD bit is set to ONE or the EEN bit is set to ZERO. If both the ESK bit and the EDI/EDO bit values are changed during one BCR19 write operation, while EEN = 1, then setup and hold times of the EEDI pin value with respect to the EESK signal edge are not guaranteed.
PREAD or
Auto Read in Progress X 1 0 0
EEN
EECS
SHFBUSY
EESK
EEDI
High Low Low Low
X X 1 0
0 Active From ECS Bit of BCR19 0
1 1 From EBUSY Bit of BCR19 PVALID
Z Active From ESK Bit of BCR19 LED1
Z Active From EEDI Bit of BCR19 LNKST
ESK has no effect on the EESK pin unless the PREAD bit is set to ZERO and the EEN bit is set to ONE. ESK is reset to ONE by H_RESET and is unaffected by S_RESET or STOP. 0 EDI/EDO EEPROM Data In/EEPROM Data Out. Data that is written to this bit will appear on the EEDI output of the microwire interface, except when the PREAD bit is set to ONE or the EEN bit is set to ZERO. Data that is read from this bit reflects the value of the E E D O i n p u t o f t h e m i c r ow i r e interface. EDI/EDO has no effect on the EEDI pin unless the PREAD bit is set to ZERO and the EEN bit is set to ONE. EDI/EDO is reset to ZERO by H_RESET and is unaffected by S_RESET or STOP. BCR20: Software Style Bit Name Description This register is an alias of the location CSR58. Accesses to/from this r egister are equivalent to accesses to CSR58. 31-10 RES Reserved locations. Written ZEROs and read as undefined. as
9
CSRPCNET CSR PCnet-ISA configuration bit. When set, this bit indicates that the PCnet-32 controller register bits of CSR4 and CSR3 will map directly to the CSR4 and CSR3 bits of the PCnet-ISA (Am79C960) device. When cleared, this bit indicates that PCnet-32 controller register bits of CSR4 and CSR3 will map directly to the CSR4 and CSR3 bits of the ILACC (Am79C900) device. The value of CSRPCNET is determined by the PCnet-32 controller. CSRPCNET is read only by the host. The PCnet-32 controller uses the setting of the Software Style register (BCR20[7:0]) to determine the value for this bit. CSRPCNET is set by H_RESET and is not affected by S_RESET or STOP.
8
SSIZE32 Software Size 32 bits. When set, this bit indicates that the PCnet-32 controller utilizes AMD79C900 (ILACC) software structures. In particular, Initialization Block and Transmit and Receive descriptor bit maps are affected. When cleared, this bit indicates that the PCnet-32 controller utilizes AMD PCnet-ISA software structures. Note: Regardless of the setting of SSIZE32, the Initialization Block
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must always begin on a double-word boundary. The value of SSIZE32 is determined by the PCnet-32 controller. SSIZE32 is read only by the host. The PCnet-32 controller uses the s e t t i n g o f t h e S o f t wa r e S t y l e register(BCR20[7:0]/CSR58[7:0]) to determine the value for this bit. SSIZE32 is cleared by H_RESET and is not affected by S_RESET or STOP. If SSIZE32 is reset, then bits IADR[31:24] of CSR2 will be used to generate values for the upper 8 bits of the 32 bit address bus during master accesses initiated by the PCnet-32 controller. This action is required, since the 16-bit software str uctures specified by the SSIZE32=0 setting will yield only 24 b i t s o f a d d r e s s fo r P C n e t - 3 2 controller bus master accesses. If SSIZE32 is set, then the software structures that are common to the PCnet-32 controller and the host system will supply a full 32 bits for each address pointer that is needed by the PCnet-32 controller for performing master accesses. The value of the SSIZE32 bit has no effect on the drive of the upper 8 address pins. The upper 8 address pins are always driven, regardless of the state of the SSIZE32 bit.
fully functional as specified in the CS R a n d B C R an d d e s c r i p to r sections. Read/write accessible only when the STOP bit is set. The SWSTLYE register will contain the value 00h following H_RESET and is not affected by S_RESET or STOP. BCR21: Interrupt Control Bit Name Description Note that all bits in this register are programmable through the EEPROM PREAD operation and software relocatable mode. 31-9 8 RES IOAW24 Reserved locations. Written ZEROs and read as undefined. as
I/O Address Width 24 bits. When set to a ONE, the IOAW24 bit will cause the PCnet-32 controller to ignore the upper 8 bits of the address bus when determining whether an I/O address matches PCnet-32 controller I/O space. When IOAW24 is set to a ZERO, then the PCnet-32 controller will examine all 32 bits of the address bus when determining whether an I/O address matches PCnet-32 controller I/O space. Read/write accessible only when the STOP bit is set. The IOAW24 bit will be reset to ZERO by H_RESET and is not affected by S_RESET or STOP.
Note:The setting of the SSIZE32 bit has no effect on the defined width for I/O resources.I/O resource width is determined by the state of the DWIO bit.
7-0 SWSTYLE Software Style register. The value in this register determines the "style" of I/O and memory resources that shall be used by the PCnet-32 controller. The Software Style selection will affect the interpretation of a few bits within the CSR space and the width of the descriptors and initialization block. See Table 53. All PCnet-32 controller CSR bits and BCR bits and all descriptor, buffer and initialization block entries not cited in the table above ar e unaffected by the Software Style selection and are therefore always
7
REJECTDIS Reject Disable. When set to a ONE, the REJECTDIS bit will cause th e E A R fu nc ti on of th e E AD I interface to be disabled. Specifically, the INTR2 pin will retain its function as INTR2 and will not function as EAR, regardless of the setting of the BCR2 EADISEL bit. When reset to a ZERO, the REJECTDIS bit will allow the INTR2 pin to be redefined to function as EAR of the EADI interface when the EADISEL bit of BCR2 has been set to a ONE. Read/write accessible only when STOP bit is set. The REJECTDIS bit will be reset to ZERO by H_RESET and is not affected by S_RESET or STOP.
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6-2 1-0
RES INTSEL
Reserved locations. Written ZEROs and read as undefined.
as
combination of INTSEL and JTAGSEL values. Interrupt pins that are not selected will be floated. The INTSEL register will contain the value 00 following H_RESET and is not affected by S_RESET or STOP.
Interrupt Select. The value of these bits determines which of the interrupt pins will be the active interrupt. Table 55 indicates which interrupt will be selected for each
Table 53. Software Style Selection
SWSTYLE[7:0] (Hex) 00 01
Style Name LANCE/ PCnet-ISA ILACC
CSRPCNET 1 0
SSIZE32 0 1
Altered Bit Interpretations ALL CSR4 bits will function as defined in the CSR4 section. TMD1[29] functions as ADD_FCS CSR4[9:8], CSR4[5:4] and CSR4[1:0] will have no function, but will be writeable and readable. CSR4[15:10], CSR4[7:6] and CSR4[3:2] will function as defined in the CSR4 section. TMD1[29] becomes NO_FCS. ALL CSR4 bits will function as defined in the CSR4 section. TMD1[29] functions as ADD_FCS Undefined
02 All other combinations
PCnet-32 Reserved
1
1
Table 54. Interrupt Select
INTSEL[1:0] 00 01 10 11 00 01 10 11 JTAGSEL 0 0 0 0 1 1 1 1 Selected interrupt Pin INTR1 INTR2 INTR3 INTR4 INTR1 INTR2 INTR1 INTR2
Initialization Block When SSIZE32=0 (BCR20/CSR58, bit 8) the software structures are defined to be 16 bits wide and the initialization block looks as shown in Table 55. When SSIZE32=1, the software structures are defined to be 32 bits wide and the initialization block looks as shown in Table 56. Regardless of the value of SSIZE32, the initialization block must be aligned to a double word boundary, i.e. CSR1[1:0] and CSR16[1:0] must be set to ZERO. Note that the PCnet-32 device performs double-word accesses to read the initialization block. This statement is always true, regardless of the setting of the SSIZE32 bit.
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Table 55. Initialization Block (when SSIZE = 0)
Address IADR+00 IADR+02 IADR+04 IADR+06 IADR+08 IADR+0A IADR+0C IADR+0E IADR+10 IADR+12 IADR+14 IADR+16 TLEN 0 RLEN 0 Bits 15-13 Bit 12 Bits 11-8 MODE 15-00 PADR 15-00 PADR 31-16 PADR 47-32 LADRF 15-00 LADRF 31-16 LADRF 47-32 LADRF 63-48 RDRA 15-00 RES TDRA 15-00 RES TDRA 23-16 RDRA 23-16 Bits 7-4 Bits 3-0
Table 56. Initialization Block (when SSIZE = 1)
Address Bits 31-28 TLEN Bits 27-24 RES Bits 23-20 RLEN Bits 19-16 RES PADR 31-00 RES LADR 31-00 LADR 63-32 RDRA 31-00 TDRA 31-00 PADR 47-32 Bits 15-12 Bits 11-8 Bits 7-4 MODE Bits 3-0
IADR+00 IADR+04 IADR+08 IADR+0C IADR+10 IADR+14 IADR+18
RLEN and TLEN When SSIZE32 = 0 (BCR20[8]), then the software structures are defined to be 16 bits wide, and the RLEN and
TLEN fields in the initialization block are 3 bits wide, occupying bits 15,14, and 13 and the value in these fields determines the number of Transmit and Receive Descriptor Ring Entries (DRE) which are used in the descriptor rings. Their meaning is shown in Table 57. Table 57. Descriptor Ring Entries (SSIZE32 = 0)
R/TLEN 000 001 010 011 100 101 110 111 No. of DREs 1 2 4 8 16 32 64 128
zation is complete. See the description of the appropriate CSRs. When SSIZE32=1 (BCR20[8]), then the software structures are defined to be 32 bits wide, and the RLEN and TLEN fields in the initialization block are 4 bits wide, occupying bits 15,14, 13, and 12, and the value in these fields determines the number of Transmit and Receive Descriptor Ring Entries (DRE) which are used in the descriptor rings. Their meaning is shown in Table 58. If a value other than those listed in the above table is desired, CSR76 and CSR78 can be written after initialization is complete. See the description of the appropriate CSRs.
If a value other than those listed in the above table is desired, CSR76 and CSR78 can be written after initiali-
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Table 58. Descriptor Ring Entries (SSIZE = 1)
R/TLEN 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 11XX 1X1X No. of DREs 1 2 4 8 16 32 64 128 256 512 512 512
must be located at 0 MOD 16 address values when SSIZE32 = 1 (BCR20[8]). Each DRE must be located at 0 MOD 8 address values when SSIZE32 = 0 (BCR20[8]). LADRF The Logical Address Filter (LADRF) is a 64-bit mask that is used to accept incoming Logical Addresses. If the first bit in the incoming address (as transmitted on the wire) is a "1", the address is deemed logical. If the first bit is a "0", it is a physical address and is compared against the physical address that was loaded through the initialization block. A logical address is passed through the CRC generator, producing a 32 bit result. The high order 6 bits of the CRC is used to select one of the 64 bit positions in the Logical Address Filter. If the selected filter bit is set, the address is accepted and the frame is placed into memory. See Figure 38.
RDRA and TDRA TDRA and RDRA indicate where the transmit and receive descriptor rings, respectively, begin. Each DRE
RECEIVED MESSAGE DESTINATION ADDRESS 47 10 1 CRC GEN SEL
32-BIT RESULTANT CRC 31 26 0 LOGICAL ADDRESS FILTER (LADRF)
63
0
MATCH=1: PACKET ACCEPTED MATCH=0: PACKET REJECTED MATCH PACKET ACCEPTED MATCH PACKET REJECTED
64 MUX MATCH
6
18219-45
Figure 38. Address Match Logic
The Logical Address Filter is used in multicast addressing schemes. The acceptance of the incoming frame based on the filter value indicates that the message may be intended for the node. It is the node's responsibility to determine if the message is actually intended for the node by comparing the destination address of the stored message with a list of acceptable logical addresses. If the Logical Address Filter is loaded with all zeroes and promiscuous mode is disabled, all incoming logical addresses except broadcast will be rejected.
The Broadcast address, which is all ones, does not go through the Logical Address Filter and is handled as follows: s If the Disable Broadcast Bit is cleared, the broadcast address is accepted s If the Disable Broadcast Bit is set and promiscuous mode is enabled, the broadcast address is accepted. s If the Disable Broadcast Bit is set and promiscuous mode is disabled, the broadcast address is rejected.
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If external loopback is used, the FCS logic must be allocated to the receiver (by setting the DXMTFCS bit in CSR15, and clearing the ADD_FCS bit in TMD1) when using multicast addressing. PADR This 48-bit value represents the unique node address assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and used for internal address comparison. PADR[0] is the first address bit transmitted on the wire, and must be zero. The six hex-digit nomenclature used by the ISO 8802-3 (IEEE/ANSI 802.3) maps to the PCnet-32 controller PADR register as follows: the first byte comprises PADR[7:0], with PADR[0] being the least significant bit of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3) byte maps to PADR[15:8], again from LS bit to MS bit, and so on. The sixth byte maps to PADR[47:40], the LS bit being PADR[40]. MODE The mode register in the initialization block is copied in to CS R15 a nd i nter pr eted ac co rd ing to th e description of CSR15. Receive Descriptors When SSIZE32 = 0 (BCR20[8]), then the software structures are defined to be 16 bits wide, and receive descriptors look as shown in Table 59.
Table 59. Receive Descriptors (SSIZE32 = 0)
LANCE/ PCnet-ISA Descriptor Designation Address CRDA+00 CRDA+02 CRDA+04 CRDA+06 Bits 15-0 RMD0 RMD1 RMD2 RMD3 PCnet-32 Descriptor Designation
Bits 15-8
Bits 7-0
RMD0[15:0] RMD1[31:24] RMD0[23:16]
RMD1[15:0] RMD2[15:0]
PCnet-32 reference names within the table above refer to the descriptor definitions given in text below. Since the text descriptions are for 32-bit descriptors, the table above shows the mapping of the 32-bit descriptors into the 16-bit descriptor space. Since 16-bit descriptors are a subset of the 32-bit descriptors, some portions of the 32-bit descriptors may not appear in Table 59. When SSIZE32 = 1 (BCR 20[8]), then the software structures are defined to be 32 bits wide, and receive descriptors look as shown in Table 60.
Table 60. Receive Descriptors (SSIZE 32 = 1)
LANCE/PCnet-ISA Descriptor Designation Address CRDA+00 CRDA+04 CRDA+08 CRDA+0C Bits 31-24 *NA RMD1[15:8] *NA *NA Bits 23-16 RMD1[7:0] *NA *NA *NA Bits 15-8 RMD0[15:8] RMD2[15:8] RMD3[15:8] *NA Bits 7-0 RMD0[7:0] RMD2[7:0] RMD3[7:0] *NA PCnet-32 Descriptor Designation Bits 31-0 RMD0 RMD1 RMD2 RMD3
* NA = These 8 bits do not exist in any LANCE descriptor.
The Receive Descriptor Ring Entries (RDREs) are composed of four receive message descriptors (RMD0- RMD3). Together they contain the following information: s The address of the actual message data buffer in user (host) memory. s The length of that message buffer. s Status information indicating the condition of the buffer. The eight most significant bits of RMD1 (RMD1[31:24]) are collectively termed the STATUS of the receive descriptor.
RMD0 Bit 31-0 Name RBADR Description RECEIVE BUFFER ADDRESS. This field contains the address of the receive buffer that is associated with this descriptor. Description This bit indicates that the descriptor entry is owned by the host (OWN=0) or by the PCnet-32 controller (OWN=1). The PCnet-32
RMD1 Bit 31 Name OWN
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controller clears the OWN bit after filling the buffer pointed to by the descriptor entry. The host sets the OWN bit after emptying the buffer. Once the PCnet-32 controller or host has relinquished ownership of a buffer, it must not change any field in the descriptor entry. 30 ERR ERR is the OR of FRAM, OFLO, CRC, or BUFF. ERR is set by the PCnet-32 controller and cleared by the host. FRAMING ERROR indicates that the incoming frame contained a non-integer multiple of eight bits and there was an FCS error. If there was no FCS error on the incoming frame, then FRAM will not be set even if there was a non integer multiple of eight bits in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only when ENP is set and OFLO is not. FRAM is set by the PCnet-32 controller and cleared by the host. OVERFLOW error indicates that the receiver has lost all or part of the incoming frame, due to an inability to store the frame in a memory buffer before the internal FIFO overflowed. OFLO is valid only when ENP is not set. OFLO is set by the PCnet-32 controller and cleared by the host. CRC indicates that the receiver has detected a CRC (FCS) error on the incoming frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the PCnet-32 controller and cleared by the host. BUFFER ERROR is set any time the PCnet-32 controller does not own the next buffer while data chaining a received frame. This can occur in either of two ways: 1. The OWN bit of the next buffer is zero. 2. FIFO overflow occurred before the PCnet-32 controller received the STATUS (RMD1[31:24]) of the next descriptor. 25 STP
If a Buffer Error occurs, an Overflow Error may also occur internally in the FIFO, but will not be reported in the descriptor status entry unless both BUFF and OFLO errors occur at the same time. BUFF is set by the PCnet-32 controller and cleared by the host. START OF PACKET indicates that this is the first buffer used by the PCnet-32 controller for this frame. It is used for data chaining buffers. S T P i s s e t by t h e P C n e t - 3 2 controller and cleared by the host. END OF PACKET indicates that this is the last buffer used by the PCnet-32 controller for this frame. It is used for data chaining buffers. If both STP and ENP are set, the frame fits not one buffer and there is no data chaining. ENP is set by the PCnet-32 controller and cleared by the host. Reserved locations. These locations should be read and written as ZEROs. These four bits must be written as ONES. They are written by the host and unchanged by the PCnet-32 controller. BUFFER BYTE COUNT is the length of the buffer pointed to by this descriptor, expressed as the two's complement of the length of the buffer. This field is written by the host and unchanged by the PCnet-32 controller. Description Receive Collision Count. Indicates the accumulated number of collisions on the network since the l a s t f r a m e wa s s u c c e s s f u l l y received, excluding collisions that occurred during transmissions from this node. The PCnet-32 controller implementation of this counter may not be compatible with the ILACC RCC definition. If network statistics are to be monitored, then CSR114 should b e u s e d fo r t h e p u r p o s e o f monitoring Receive collisions instead of these bits.
29
FRAM
24
ENP
23-16 RES
28
OFLO
15-12 ONES
11-0
BCNT
27
CRC
RMD2 Bit Name 31-24 RCC
26
BUFF
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23-16 RPC
Runt Packet Count. Indicates the accumulated number of runts that were addressed to this node since the last time that a receive packet was successfully received and its corresponding RMD2 ring entry was written to by the PCnet-32 controller. In order to be included in the RPC value, a runt must be long enough to meet the minimum requirement of the internal address matching logic. The minimum requirement for a runt to pass the internal address matching mechanism is: 18 bits of valid preamble plus a valid SF D detected, followed by 7 bytes of frame data. This requirement is u nva r y i n g , r e g a r d l e s s o f t h e address matching mechanisms in force at the time of reception (i.e. physical, logical, broadcast or pr omi sc uo us) . The P Cnet -3 2 controller implementation of this counter may not be compatible with the ILACC RPC definition. This field is reserved. PCnet-32 controller will write ZEROs to these locations. MESSAGE Byte COUNT is the length in bytes of the received message, expressed as an unsigned binary integer. MCNT is valid only when ERR is clear and ENP is set. MCNT is written by the
PCnet-32 controller and cleared by the host. RMD3 Bit 31-0 Name RES Description Reserved locations. All bits must be ZEROs.
Transmit Descriptors
When SSIZE32 = 0 (BCR 20[8]), then the software structures are defined to be 16 bits wide, and transmit descriptors look as shown in Table 61. PCnet-32 reference names within the table above refer to the descriptor definitions given in text below. Since the text descriptions are for 32-bit descriptors, the table above shows the mapping of the 32-bit descriptors into the 16-bit descriptor space. Since 16-bit descriptors are a subset of the 32-bit descriptors, some portions of the 32-bit descriptors may not appear in Table 61. When SSIZE32 = 1 (BCR 20[8]), then the software structures are defined to be 32 bits wide, and transmit descriptors look as shown in Table 62.
Table 61. Transmit Descriptor (SSIZE32 = 0)
LANCE Descriptor Designation Address CRDA+00 CRDA+02 CRDA+04 CRDA+06 Bits 15-0 TMD0 TMD1 TMD2 TMD3 PCnet-32 Descriptor Designation Bits 15-8 Bits 7-0
15-12 ZEROs
11-0
MCNT
TMD0[15:0] TMD1[31:24] TMD0[23:16]
TMD1[15:0] TMD2[15:0]
Table 62. Transmit Descriptor (SSIZE32 = 1)
LANCE Descriptor Designation Address CTDA+00 CTDA+04 CTDA+08 CTDA+0C Bits 31-24 *NA TMD1[15:8] TMD3[15:8] *NA Bits 23-16 TMD1[7:0] *NA TMD3[7:0] *NA Bits 15-8 TMD0[15:8] TMD2[15:8] *NA *NA Bits 7-0 TMD0[7:0] TMD2[7:0] *NA *NA PCnet-32 Descriptor Designation Bits 31-0 TMD0 TMD1 TMD2 TMD3
* NA = These 8 bits do not exist in any LANCE descriptor.
The Transmit Descriptor Ring Entries (TDREs) are composed of 4 transmit message descriptors (TMD0T M D 3 ) . To g e t h e r t h ey c o n t a i n t h e fo l l o w i n g information: s The address of the actual message data buffer in user or host memory.
s The length of the message buffer. s Status information indicating the condition of the buffer. The eight most significant bits of TMD1 (TMD1[31:24]) are collectively termed the STATUS of the transmit descriptor.
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TMD0 Bit 31-0 Name TBADR Description Transmit Buffer address. This field contains the address of the transmit buffer that is associated with this descriptor. Description This bit indicates that the descriptor entry is owned by the host (OWN=0) or by the PCnet-32 controller (OWN=1). The host sets the OWN bit after filling the buffer pointed to by the descriptor entry. The PCnet-32 controller clears the OWN bit after transmitting the contents of the buffer. Both the PCnet-32 controller and the host must not alter a descriptor entry after it has relinquished ownership. ER is the OR of UFLO, LCOL, LCAR, or RTRY. ERR is set by the PCnet-32 controller and cleared by the host. This bit is set in the current descriptor when the error occurs, and therefore may be set in any descriptor of a chained buffer transmission.
NO_FCS
TMD1 Bit 31 Name OWN
NO_FCS dynamically controls the generation of FCS on a frame by frame basis. It is valid only if the ENP bit is set. When NO_FCS is set, the state of DXMTFCS is i gn or ed an d tran s mi tt er FCS generation is deactivated. When NO_FCS = 0, FCS generation is controlled by DXMTFCS. NO_FCS is set by the host, and unchanged by the PCnet-32 controller. This was a reserved bit in the LANCE (Am7990). This function is identi cal to the ILACC function for this bit. MORE indicates that more than one retry was needed to transmit a frame. The value of MORE is written by the PCnet-32 controller. This bit has meaning only if the ENP bit is set. ONE indicates that exactly one retry was needed to transmit a frame. ONE flag is not valid when LCOL is set. The value of the ONE bit is written by the PCnet-32 controller. This bit has meaning only if the ENP bit is set. DEFERED indicates that the PCnet-32 controller had to defer while trying to transmit a frame. This condition occurs if the channel is busy when the PCnet-32 controller is ready to transmit. DEF is set by the PCnet-32 controller and cleared by the host. START OF PACKET indicates that this is the first buffer to be used by the PCnet-32 controller for this frame. It is used for data chaining buffers. The STP bit must be set in the first buffer of the frame, or the PCnet-32 controller will skip over the descriptor and poll the next descriptor(s) until the OWN and STP bits are set. STP is set by the host and unchanged by the PCnet-32 controller.
28
MORE
30
ERR
27
ONE
26
DEF
29
ADD_FCS/NO_FCS Bit 29 functions as ADD_FCS when programmed for the default I/O style of PCnet-ISA and when programmed for the I/O style P C n e t - 3 2 c o n t r o l l e r. B i t 2 9 functions as NO_FCS when programmed for the I/O style ILACC. ADD_FCS ADD_FCS dynamically controls the generation of FCS on a frame by frame basis. It is valid only if the STP bit is set. When ADD_FCS is set, the state of DXMTFCS is ig no r ed an d t ran s mi tte r FCS generation is activated. When ADD_FCS = 0, FCS generation is controlled by DXMTFCS. ADD_FCS is set by the host, and u n c h a n g e d by t h e P C n e t - 3 2 controller. This was a reserved bit in the LANCE (Am7990). This function differs from the ILACC function for this bit.
25
STP
24
ENP
END OF PACKET indicates that this is the last buffer to be used by the PCnet-32 controller for this frame. It is used for data chaining buffers. If both STP and ENP are set, the frame fits into one buffer
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and there is no data chaining. ENP is set by the host and unchanged by the PCnet-32 controller. 23-16 RES 15-12 ONES Reserved locations. Must be Ones. This field is written by the host and unchanged by the PCnet-32 controller. BUFFER BYTE COUNT is the usable length of the buffer pointed to by this descriptor, expressed as the two's complement of the length of the buffer. This is the number of bytes from this buffer that will be t ra n s m i t t ed by t h e P C n e t- 3 2 controller. This field is written by the host and unchanged by the PCnet-32 controller. There are no minimum buffer size restrictions. Description BUFFER ERROR is set by the PCnet-32 controller during transmission when the PCnet-32 controller does not find the ENP flag in the current buffer and does not own the next buffer. This can occur in either of two ways: 1. The OWN bit of the next buffer is zero. 2. FIFO underflow occurred before the PCnet-32 controller obtained the STATUS byte (TMD1[31:24]) of the next descriptor. BUFF is set by the PCnet-32 controller and cleared by the host. BUFF error will turn off the transmitter (CSR0, TXON = 0). If a Buffer Error occurs, an Underflow Error will also occur. BUFF is not valid when LCOL or RTRY error is set during transmit data chaining. BUFF is set by the PCnet-32 controller and cleared by the host. 30 UFLO UNDERFLOW ERROR indicates that the transmitter has truncated a message due to data late from memory. UFLO indicates that the FIFO has emptied before the end of the frame was reached. Upon UFLO error, the transmitter is tur ned off (CSR0, TXON = 0).
UFLO is set by the PCnet-32 controller and cleared by the host. 29 EXDEF EXCESSIVE DEFERRAL. Indicates that the transmitter has experienced Excessive Deferral on this transmit frame, where Excessive Deferral is defined in ISO 8802-3 (IEEE/ANSI 802.3).
11-0
BCNT
28
LCOL LATE COLLISION indicates that a collision has occurred after the slot time of the channel has elapsed. The PCnet-32 controller does not retry on late collisions. LCOL is set by the PCnet-32 controller and cleared by the host. LCAR LOSS OF CARRIER is set in AUI mode when the carrier is lost during an PCnet-32 controllerinitiated transmission. The PCnet-32 controller does not re-try upon loss of carrier. It will continue to transmit the whole frame until done. In 10BASE-T mode LCAR will be set when the T-MAU is in Link Fail state. LCAR is not valid in Internal Loopback Mode. LCAR is set by the PCnet-32 controller and cleared by the host. RETRY ERROR indicates that the transmitter has failed after 16 attempts to successfully transmit a message, due to repeated collisions on the medium. If DRTY = 1 in the MODE register, RTRY will set after 1 failed transmission a t t e m p t . RT RY i s s e t by t h e PCnet-32 controller and cleared by the host. TIME DOMAIN REFLECTOMETRY reflects the state of an inter nal PCnet-32 controller counter that counts at a 10 MHz rate from the start of a transmission to the occurrence of a collision or loss of carrier. This value is useful in deter mining the approximate distance to a cable fault. The TDR value is written by the PCnet-32 controller and is valid only if RTRY is set. Note that 10 MHz gives very low resolution and in general has not been found to be par ticular ly u s e f u l . T h i s fe a t u r e i s h e r e primarily to maintain full
27
TMD2 Bit 31 Name BUFF
26
RTRY
25-16 TDR
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compatibility with the LANCE (Am7990). 15-4 3-0 RES TRC Reserved locations. TRANSMIT RETRY COUNT. Indicates the number of transmit retries of the associated packet. The maximum count is 15. However, if a RETRY error occurs, the count will roll over to zero. In this case only, the Transmit Retr y
Count value of zero should be interpreted as meaning 16. TRC is written by the PCnet-32 controller into the last transmit descriptor of a frame, or when an error terminates a frame. Valid only when OWN = 0. TMD3 Bit 31-0 Name RES Description Reserved locations. All bits must be ZEROs.
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REGISTER SUMMARY
CSRs -- Control and Status Registers
RAP Addr 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 Symbol Default Value After H_RESET (Hex) xxxx 0004 xxxx xxxx xxxx xxxx xxxx 0000 xxxx 0115 xxxx 0000 xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx See Register Desc. xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Comments Use
CSR0 CSR1 CSR2 CSR3 CSR4 CSR5 CSR6 CSR7 CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR16 CSR17 CSR18 CSR22 CSR20 CSR21 CSR22 CSR23 CSR24 CSR25 CSR27 CSR28 CSR29 CSR30 CSR31 CSR32 CSR33 CSR34 CSR35 CSR36
PCnet-32 Controller Status Lower IADR: maps to location 16 Upper IADR: maps to location 17 Interrupt Masks and Deferral Control Test and Features Control Reserved RXTX: RX/TX Descriptor Table Length Reserved LADR0: Logical Address Filter -- LADRF[15:0] LADR1: Logical Address Filter -- LADRF[31:16] LADR2: Logical Address Filter -- LADRF[47:32] LADR3: Logical Address Filter -- LADRF[63:48] PADR0: Physical Address Register -- PADR[15:0][ PADR1: Physical Address Register -- PADR[31:16] PADR2: Physical Address Register -- PADR[47:32] MODE: Mode Register IADR: Base Address of INIT Block Lower (Copy) IADR: Base Address of INIT Block Upper (Copy) CRBA: Current RCV Buffer Address Lower CRBA: Current RCV Buffer Address Upper CXBA: Current XMT Buffer Address Lower CXBA: Current XMT Buffer Address Upper NRBA: Next RCV Buffer Address Lower NRBA: Next RCV Buffer Address Upper BADR: Base Address of RCV Ring Lower BADR: Base Address of RCV Ring Upper NRDA: Next RCV Descriptor Address Upper CRDA: Current RCV Descriptor Address Lower CRDA: Current RCV Descriptor Address Upper BADX: Base Address of XMT Ring Lower BADX: Base Address of XMT Ring Upper NXDA: Next XMT Descriptor Address Lower NXDA: Next XMT Descriptor Address Upper CXDA: Current XMT Descriptor Address Lower CXDA: Current XMT Descriptor Address Upper NNRDA: Next Next Receive Descriptor Address Lower
R S S S R T T T T T T T T T T S T T T T T T T T S S T T T S S T T T T T
Key:
x = undefined
R = Running Register
S = Setup Register
T = Test Register
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REGISTER SUMMARY (continued)
CSRs -- Control and Status Registers
RAP Addr 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol Default Value After H_RESET (Hex) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx See Register Desc. xxxx 0105 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Comments Use
CSR37 CSR38 CSR39 CSR40 CSR41 CSR42 CSR43 CSR44 CSR45 CSR46 CSR47 CSR48 CSR48 CSR50 CSR50 CSR52 CSR52 CSR54 CSR54 CSR56 CSR56 CSR58 CSR59 CSR60 CSR61 CSR62 CSR63 CSR64 CSR65 CSR66 CSR67 CSR68 CSR69 CSR70 CSR71 CSR72
NNRDA: Next Next Receive Descriptor Address Upper NNXDA: Next Next Transmit Descriptor Address Lower NNXDA: Next Next Transmit Descriptor Address Upper CRBC: Current RCV Status and Byte Count Lower CRBC: Current RCV Status and Byte Count Upper CXBC: Current XMT Status and Byte Count Lower CXBC: Current XMT Status and Byte Count Upper NRBC: Next RCV Status and Byte Count Lower NRBC: Next RCV Status and Byte Count Upper POLL: Poll Time Counter PI: Polling Interval TMP2: Temporary Storage Lower TMP2: Temporary Storage Upper TMP3: Temporary Storage Lower TMP3: Temporary Storage Upper TMP4: Temporary Storage Lower TMP4: Temporary Storage Upper TMP5: Temporary Storage Lower TMP5: Temporary Storage Upper TMP6: Temporary Storage Lower TMP6: Temporary Storage Upper SWS: Software Style IR: IR Register PXDA: Previous XMT Descriptor Address Lower PXDA: Previous XMT Descriptor Address Upper PXBC: Previous XMT Status and Byte Count Lower PXBC: Previous XMT Status and Byte Count Upper NXBA: Next XMT Buffer Address Lower NXBA: Next XMT Buffer Address Upper NXBC: Next XMT Status and Byte Count Lower NXBC: Next XMT Status and Byte Count Upper XSTMP: XMT Status Temporary Storage Lower XSTMP: XMT Status Temporary Storage Upper RSTMP: RCV Status Temporary Storage Lower RSTMP: RCV Status Temporary Storage Upper RCVRC: RCV Ring Counter
T T T T T T T T T T S T T T T T T T T T T S T T T T T T T T T T T T T T
Key:
x = undefined
R = Running Register
S = Setup Register
T = Test Register
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REGISTER SUMMARY
CSRs -- Control and Status Registers (continued)
RAP Addr 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Symbol Default Value After H_RESET (Hex) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx E810 xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0243 0003 xxxx 0243 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0200 xxxx xxxx xxxx xxxx xxxx 0105 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Comments Use
CSR73 CSR74 CSR75 CSR76 CSR77 CSR78 CSR79 CSR80 CSR81 CSR82 CSR83 CSR84 CSR85 CSR86 CSR87 CSR88 CSR89 CSR90 CSR91 CSR92 CSR93 CSR94 CSR95 CSR96 CSR97 CSR98 CSR99 CSR100 CSR101 CSR102 CSR103 CSR104 CSR105 CSR106 CSR107 CSR108 CSR109
Reserved XMTRC: XMT Ring Counter Reserved RCVRL: RCV Ring Length Reserved XMTRL: XMT Ring Length Reserved Burst and FIFO Threshold Control Reserved DMABAT: Bus Acitivty Timer Reserved DMABA: DMA Address Lower DMABA: DMA Address Upper DMABC: Buffer Byte Counter Reserved Chip ID Lower Chip ID Upper Reserved Reserved RCON: Ring Length Conversion Reserved XMTTDR: Transmit Time Domain Reflectometry Count Reserved SCR0: BIU Scratch Register 0 Lower SCR0: BIU Scratch Register 0 Upper SCR1: BIU Scratch Register 1 Lower SCR1: BIU Scratch Register 1 Upper Bus Time-Out Reserved Reserved Reserved SWAP: Swap Register Lower SWAP: Swap Register Upper Reserved Reserved BMSCR: BMU Scratch Register Lower BMSCR: BMU Scratch Register Upper
T T T S T S T S T S T T T T T T T T T T T T T T T T T S T T T T T T T T T
Key:
x = undefined
R = Running Register
S = Setup Register
T = Test Register
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REGISTER SUMMARY (continued)
CSRs -- Control and Status Registers
RAP Addr 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Symbol Default Value After H_RESET (Hex) xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx See Register Desc. xxxx xxxx See Register Desc. xxxx xxxx xxxx xxxx xxxx xxxx Comments Use
CSR110 CSR111 CSR112 CSR113 CSR114 CSR115 CSR116 CSR117 CSR118 CSR119 CSR120 CSR121 CSR122 CSR123 CSR124 CSR125 CSR126 CSR127
Reserved Reserved Missed Frame Count Reserved Receive Collision Count Reserved Reserved Reserved Reserved Reserved Reserved Reserved Receive Frame Alignment Control Reserved BMU Test Reserved Reserved Reserved
T T R T R T T T T T T T S T T T T T
Key:
x = undefined
R = Running Register
S = Setup Register
T = Test Register
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REGISTER SUMMARY
BCR -- Bus Configuration Registers
RAP Addr. 0 1 2 3 4 5 6 7 8-15 16 17 18 19 20 21 Mnemonic Default (Hex) 0005 0005 N/A* N/A 00C0 0084 0088 0090 N/A N/A* N/A* 2101 0002 0000 N/A* I/O Base Address Lower I/O Base Address Upper Burst Size and Bus Control EEPROM Control and Status Software Style Interrupt Control Link Status (Default) Receive (Default) Receive Polarity (Default) Transmit (Default) Name User Master Mode Read Active Master Mode Write Active Miscellaneous Configuration No No Yes No Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Programmability EEPROM No No Yes No No No No No No Yes Yes Yes No No Yes SRM No No Yes No No No No No No Yes Yes No No No Yes
MSRDA MSWRA MC Reserved LNKST LED1 LED2 LED3 Reserved IOBASEL IOBASEU BSBC EECAS SWSTYLE INTCON
Key: SRM = Software Relocatable Mode * Registers marked with an asterisk (*) have no default value, since they are not observable without first being programmed, either through
the EEPROM read operation or through the Software Relocatable Mode. Therefore, the only observable values for these registers are those that have been programmed and a default value is not applicable.
AM79C965A
183
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................... -65C to +150C Ambient Temperature Under Bias ..................................... -65C to +125C Supply Voltage to AVSS or DVSS (AVDD, DVDD)..................... -0.3 V to +6.0 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Temperature (TA) ................................. 0C to +70C Supply Voltages (AVDD, DVDD) ..............................................5 V 5% All inputs within the range: ....... AVSS - 0.5 V Vin AVDD + 0.5 V, or DVSS - 0.5 V Vin DVDD + 0.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol Digital Input Voltage VIL VIH Input LOW Voltage Input HIGH Voltage 2.0 0.8 V V Parameter Description Test Conditions Min Max Unit
Digital Ouput Voltage VOL VOH Output LOW Voltage Output HIGH Voltage (Note 2) Input Leakage Current (Note 3) Output Low Leakage Current (Note 4) Output High Leakage Current (Note 4) XTAL1 Input LOW Threshold Voltage XTAL1 Input HIGH Threshold Voltage XTAL1 Input LOW Current IOL1 = 8 mA, IOL2 = 4 mA (Notes 1 and 5) IOH = -4 mA (Note 5) 2.4 0.45 V V
Digital Input Leakage Current IIX VDD = 5 V, VIN = 0 V
-10 -10
10
A
Digital Ouput Leakage Current IOZL IOZH Crystal Input VILX VILHX IILX VIN = External Clock VIN = External Clock VIN = 0 V VOUT = 0 V VOUT = VDD
A
10
A
-0.5
VDD-0.8
0.8 VDD + 0.5 0 +10 120 400
V V
Active Sleep
-120 -10
0
A A A A A A
mV mV
IIHX
XTAL1 Input HIGH Current
VIN = VDD
Active Sleep
Attachment Unit Interface IIAXD IIAXC VAOD VAODOFF Input Current at DI+ and DI- Input Current at CI+ and CI- Differential Output Voltage |(DO+)-(DO-)| Transmit Differential Output Idle Voltage
-1 V < VIN < AVDD +0.5 V -1 V < VIN < AVDD
RL = 78 RL = 78 (Note 9) +0.5 V
-500 -500
630
+500 +500 1200 +40
-40
184
AM79C965A
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued)
Parameter Symbol Parameter Description Test Conditions Min Max Unit
Attachment Unit Interface (Continued) IAODOFF VCMT VODI VATH VASQ VIRDVD VICM VOPD Transmit Differential Output Idle Current Transmit Output Common Mode Voltage DO Transmit Differential Output Voltage Imbalance Receive Data Differential Input Threshold DI and CI Differential Input Threshold (Squelch) DI and CI Differential Mode Input Voltage Range DI and CI Input Bias Voltage DO Undershoot Voltage at Zero Differential on Transmit Return to Zero (ETD) IIN = 0 mA (Note 9) RL = 78 (Note 8) RL = 78 RL = 78 (Note 7)
-1
2.5
+1 AVDD 25 35
mA V mV mV mV V V mV
-35 -275 -1.5
AVDD-3.0
-160
+1.5 AVDD-1.0
-100
Twisted Pair Interface IIRXD RRXD VTIVB VTIDV VTSQ+ VTSQ- VTHS+ VTHS- VLTSQ+ VLTSQ- VLTHS+ VLTHS- Input Current at RXD RXD Differential Input Resistance RXD+, RXD- Open Circuit Input Voltage (Bias) Differential Mode Input Voltage Range (RXD) RXD Positive Squelch Threshold (Peak) RXD Negative Squelch Threshold (Peak) RXD Post-Squelch Positive Threshold (Peak) RXD Post-Squelch Negative Threshold (Peak) RXD Positive Squelch Threshold (Peak) RXD Negative Squelch Threshold (Peak) RXD Post-Squelch Positive Threshold (Peak) RXD Post-Squelch Negative Threshold (Peak) Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz Sinusoid 5 MHz f 10 MHz LRT = LOW LRT = LOW LRT = LOW LRT = LOW 300 520 mV mV mV mV mV mV mV mV IIN = 0 mA AVDD = 5 V AVSS < VIN < AVDD
-500
10
500
A
K
AVDD
- 3.0
AVDD - 1.5 +3.1
V V
-3.1
-520
150
-300
293
-293
180
-150
312
-312
90
-180
176
-176
-90
AM79C965A
185
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued)
Parameter Symbol Parameter Description Test Conditions Min Max Unit
Twisted Pair Interface (continued) VRXDTH VTXH VTXL VTXI RXD Switching Threshold TXD and TXP Output HIGH Voltage TXD and TXP Output LOW Voltage TXD and TXP Differential Output Voltage Imbalance TXD and TXP Idle Output Voltage TXD Differential Driver Output Impedance TXP Differential Driver Output Impedance IEEE 1149.1 (JTAG) Test Port VIL VIH VOL VOH IIL IIH IOZ TCK, TMS, TDI TCK, TMS, TDI TDO TDO TCK, TMS, TDI TCK, TMS, TDI TDO IOL = 2.0 mA IOH = -0.4 mA VDD = 5.5 V, VI = 0.5 V VDD =5.5 V, VI = 2.7V VOUT = 0 V, VOUT = VDD 2.4 2.0 0.4 0.8 V V V V (Note 4) (Note 4) (Note 4) DVSS = 0 V DVDD = +5 V
-35
DVDD - 0.6 DVSS
35 DVDD
mV V V mV
DVSS + 0.6 +40
-40
VTXOFF RTX
40 40 80
mV

-200 -100 -10
+10
A A A
Power Supply Current IDD IDDCOMA IDDSNOOZE Pin Capacitance CIN CO CCLK Input Pin Capacitance I/O or Output Pin Capacitance BCLK Pin Capacitance FC = 1 MHz (Note 6) FC = 1 MHz (Note 6) FC = 1 MHz (Note 6) 10 10 10 pF pF pF Active Power Supply Current Coma Mode Power Supply Current Snooze Mode Power Supply Current XTAL1 = 20 MHz SLEEP active AWAKE bit set active 100 200 10 mA
A
mA
Notes:
1. IOL1 = 8 mA applies to all output and I/O pins except HOLD and LDEV. IOL2 = 4 mA applies to HOLD and LDEV only. 2. VOH does not apply to open-drain output pins. 3. IIX applies to all input only pins except DI, CI, and XTAL1. 4. IOZL and IOZH apply to all three-state output pins and bi-directional pins. 5. Outputs are CMOS and will be driven to rail if the load is not resistive. 6. Parameter not tested; value determined by characterization. 7. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands. 8. Correlated to other tested parameters - not tested directly. 9. Test not implemented to data sheet specification.
186
AM79C965A
SWITCHING CHARACTERISTICS: BUS INTERFACE
Parameter Symbol Clock Timing CLK Frequency t1 t2 t3 t4 t5 CLK Period CLK High time CLK Low Time CLK Fall Time CLK Rise Time @ 2.0 V @ 0.8 V 2.0 V to 0.8 V (Note 1) 0.8 V to 2.0 V (Note 1) 1 30 14 14 3 3 33 1000 MHz ns ns ns ns ns Parameter Description Test Conditions (CL = 50 pF Unless Otherwise Noted) Min Max Unit
Output and Float Delay Timing t6 A2-A31, BE0-BE3, M/IO, D/C, W/R, ADS, HOLD, HLDAO, INTR, EADS, RDY Valid Delay A2-A31, BE0-BE3, M/IO, D/C, W/R, ADS, RDY Float Delay 3 12 ns
t7
18
ns
t8 t8a t9 t10 t11 t12 t13 BLAST Valid Delay BLAST Float Delay D0-D31 Data Valid Delay D0-D31 Data Float Delay (This symbol is not used) (This symbol is not used) 3 3 12 18 12 18
ns ns ns ns ns
Setup and Hold Timing t14 t15 t16 t17 t18 t18a t19 t20 t21 t22 LBS16 Setup time LBS16 Hold Time BRDY, RDYRTN Setup Time BRDY, RDYRTN Hold Time HOLDI, AHOLD, HLDA, SLEEP Setup Time BOFF Setup Time HOLDI, BOFF, AHOLD, HLDA, SLEEP Hold Time RESET, CLKRESET Setup Time RESET, CLKRESET Hold Time D0-D31, A2-A31, BE0-BE3, ADS, M/IO, D/C, W/R Setup Time D0-D31, A2-A31, BE0-BE3, ADS, M/IO, D/C, W/R Hold Time 5 2 5 2 6 8 2 5 2 4 ns ns ns ns ns ns ns ns ns ns
t23
2
ns
AM79C965A
187
SWITCHING CHARACTERISTICS: BUS INTERFACE (CONTINUED)
Parameter Symbol Parameter Description Test Conditions (CL = 50 pF Unless Otherwise Noted) Min Max Unit
JTAG (IEEE 1149.1) Test Signal Timing t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 LDEV Timing t38 t39 ADS Asserted to LDEV Asserted LDEV Valid Pulse Width tBCLK 20 ns TCK Frequency TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay All Inputs (Non-Test)) Setup Time All Inputs (Non-Test) Hold Time 8 7 3 16 10 3 60 50 25 36 @ 2.0 V @ 0.8 V 100 45 45 4 4 10 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Bus Activation Timing (Slave) t40 Data Bus Driven After ADS Sampled Asserted 1 BCLK
HOLD Inactive Timing t41 EEPROM Timing t42 t43 t44 t45 t46 t47 t48 EESK Frequency EESK HIGH Time EESK LOW Time EECS, EEDI, SHFBUSY Valid Output Delay from EESK EECS LOW Time EEDO Setup Time to EESK EEDO Hold Time to EESK (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 780 780 650 kHz ns ns +15 ns ns ns ns HOLD Deasserted to HOLD Asserted 2 BCLK -15 ns
-15
1550 50 0
Notes: 1. Not 100% tested; guaranteed by design characterization. 2. Parameter value is given for automatic EEPROM read operation. When EEPROM port (BCR19) is used to access the EEPROM, software is responsible for meeting EEPROM timing requirements.
188
AM79C965A
SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE
Parameter Symbol Transmit Timing tTETD tTR tTF tTM tPERLP tPWLP tPWPLP tJA tJR tJREC Transmit Start of Idle Transmitter Rise Time Transmitter Fall Time Transmitter Rise and Fall Time Mismatch Idle Signal Period Idle Link Pulse Width Predistortion Idle Link Pulse Width Transmit Jabber Activation Time Transmit Jabber Reset Time Transmit Jabber Recovery Time (minimum time gap between transmitted frames to prevent jabber activation) (Note 1) (Note 1) 8 75 45 20 250 1.0 (10% to 90%) (90% to 10%) 250 350 5.5 5.5 1 24 120 55 150 750 ns ns ns ns ms ns ns ms ms Parameter Description Test Conditions Min Max Unit
s
Receive Timing tPWNRD tPWROFF tRETD tRCVON tRCVOFF RXD Pulse Width Not to Turn Off Internal Carrier Sense RXD Pulse Width to Turn Off Receive Start of Idle RCV Asserted Delay RCV De-Asserted Delay VIN > VTHS (min) VIN > VTHS (min) 200 TRON - 50 20 TRON + 100 62 136
-
200
ns ns ns ns ms
Collision Detection and SQE Test tCOLON tCOLOFF COL Asserted Delay COL De-Asserted Delay 750 20 900 62 ns ms
Note: 1. Not tested; parameter guaranteed by characterization.
AM79C965A
189
SWITCHING CHARACTERISTICS: AUI
Parameter Symbol AUI Port tDOTR tDOTF tDORM tDOETD tPWODI tPWKDI tPWOCI tPWKCI DO+,DO- rise time (10% to 90%) DO+,DO- fall time (90% to 10%) DO+,DO- rise and fall time mismatch DO+/- End of Transmission DI pulse width accept/reject threshold DI pulse width maintain/turn-off threshold CI pulse width accept/reject threshold CI pulse width maintain/turn-off threshold |VIN| > |VASQ| (Note 1) |VIN| > |VASQ| (Note 2) |VIN| > |VASQ| (Note 3) |VIN| > |VASQ| (Note 4) 2.5 2.5 5.0 5.0 1.0 375 45 200 26 160 ns ns ns ns ns ns ns ns Parameter Description Test Conditions Min Max Unit
-
200 15 136 10 90
Internal MENDEC Clock Timing tX1 tX1H tX1L tX1R tX1F XTAL1 period XTAL1 HIGH pulse width XTAL1 LOW pulse width XTAL1 rise time XTAL1 fall time VIN = External Clock VIN = External Clock VIN = External Clock VIN = External Clock VIN = External Clock 49.995 20 20 5 5 50.005 ns ns ns ns ns
Notes: 1. 2. 3. 4. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turn internal DI carrier sense off. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turn internal CI carrier sense off.
190
AM79C965A
SWITCHING CHARACTERISTICS: GPSI
Parameter Symbol Transmit Timing tGPT1 tGPT2 tGPT3 tGPT4 tGPT5 tGPT6 tGPT7 tGPT8 STDCLK period (802.3 Compliant) STDCLK High Time TXDAT and TXEN delay from STDCLK RXCRS setup before STDCLK (Last Bit) RXCRS hold after TXEN CLSN active time to trigger collision CLSN active to RXCRS to prevent LCAR assertion CLSN active to RXCRS for SQE Hearbeat Window tGPT9 Receive Timing tGPR1 tGPR2 tGPR3 tGPR4 tGPR5 tGPR6 tGPR7 tGPR8 tGPR9 tGPR10 tGPR11 tGPR12 SRDCLK period SRDCLK High Time SRDCLK Low Time RXDAT and RXCRS setup to SRDCLK RXDAT hold after SRDCLK RXCRS hold after SRDCLK CLSN active to first SRDCLK (Collision Recognition) CLSN active to SRDCLK for Address Type Designation Bit CLSN setup to last SRDCLK for Collision Recognition CLSN active CLSN inactive setup to first SRDCLK CLSN inactive hold to last SRDCLK (Note 3) (Note 2) (Note 2) (Note 2) 80 30 30 15 15 0 0 51.2 210 110 300 300 120 80 80 ns ns ns ns ns ns ns CLSN active to RXCRS for normal collision 0 51.2 (Note 1) 99.99 40 0 210 0 110 0 0 4.0 100.01 60 70 ns ns ns ns ns ns ns Parameter Description Test Conditions Min Max Unit
s
s
s
ns ns ns ns
Notes: 1. 2. 3. CLSN must be asserted for a continuous period of 110 nsec or more. Assertion for less than 110 nsec period may or may not result in CLSN recognition. RXCRS should meet jitter requirements of IEEE 802.3 specification. CLSN assertion before 51.2 msec will be indicated as a normal collision. CLSN assertion after 51.2 msec will be considered as a Late Receive Collision.
AM79C965A
191
SWITCHING CHARACTERISTICS: EADI
Parameter Symbol tEAD1 tEAD2 tEAD3 tEAD4 tEAD5 tEAD6 Parameter Description SRD setup to SRDCLK SRD hold to SRDCLK SF/BD change to SRDCLK EAR de-assertion to SRDCLK (first rising edge) EAR assertion after SFD event (packet rejection) EAR assertion Test Conditions Min 40 40 Max Unit ns ns +15 ns ns 51,090 ns ns
-15
50 0 110
192
AM79C965A
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H Don't Care Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is High Impedance Off" State
KS000010
SWITCHING TEST CIRCUITS
IOL
Sense Point CL
VTHRESHOLD
IOH
18219-46
Normal and Three-State Outputs
AM79C965A
193
SWITCHING TEST CIRCUITS
AVDD
52.3 DO+ DO100 pF 154 Test Point
AV
18219-47
AUI DO Switching Test Circuit
DVDD
294 TXD+ TXD100 pF Includes Test Jig Capacitance 294 Test Point
DVSS
18219-48
TXD Switching Test Circuit
DVDD
715 TXP+ TXP100 pF Includes Test Jig Capacitance 715 Test Point
DVSS
18219-49
TXP Outputs Test Circuit
194
AM79C965A
ESTIMATED OUTPUT VALID DELAY VS. LOAD CAPACITANCE
Note that this graph represents change in output delay for estimated conditions.
MAX+6 Maximum output delay (ns)
MAX+4
MAX+2
MAX
MAX-D2 25 50 75 100 125 150 CL (pF)
Notes: This graph will not be linear outside of the CL range shown. MAX = maximum value given in A.C. characteristics table.
18219-50
Output Delay Versus Load Capacitance Under Estimated Conditions
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
t2 2.0V 1.5V 0.8V t5 t1 t4
BCLK
t3 0.8V
18219-51
BLCK Waveform
AM79C965A
195
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
Tx
BCLK
Tx
Tx
t6
A2-A31, BE0-BE3 M/IO, , D/C, W/R, ADS, HOLD, HLDAO, INTR, RDY, EADS
Min
Max Valid n+1
Valid n t10 Valid n t8a
Min
Max Valid n+1
D0-D31
Min
Max Valid n+1
18219-52
BLAST
Valid n
Output Valid Delay Timing
Tx
BCLK
Tx
Tx
t6
A2-A31, BE0-BE3 M/IO, , D/C, W/R, ADS
Min
t7
Valid n t10 t11
Min
D0-D31
Valid n t8a t9
Min
BLAST
Valid n
18219-53
Maximum Float Delay Timing
196
AM79C965A
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
Tx
BCLK
Tx
t14
LBS16
t15
t18
HOLDI, AHOLD, HLDA, SLEEP
t19
t20
RESET, CLKRESET
t21
t22
A2-A31, BE0-BE3 , ADS, D/C, M/IO, W/R
t23
t18a
BOFF
t19
18219-54
Input Setup and Hold Timing
T2
BCLK
Tx
t16
RDY, BRDY, RDYRTN
t17
t22
D0-D31
t23
18219-55
Ready Data Setup and Hold Timing
AM79C965A
197
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
t26 2.0V 1.5V 0.8V t28 t25 t29
TCK
t27 0.8V
18219-56
JTAG (IEEE 1149.1) TCK Waveform
t25
TCK
t30
TDI, TMS
t31
t32
TDO
t33
t34
Output Signals
t35
t36
Input Signals
t37
18219-57
JTAG (IEEE 1149.1) Test Signal Timing
198
AM79C965A
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
Tx
BCLK
Tx
Tx
A2-A31, BE0-BE3 , M/IO, D/C, W/R, RDY
Valid PCnet-32 Address
ADS
t38
LDEV
Min
Max
t39
D0-D31
Valid PCnet-32 Data t40
18219-58
LDEV Timing and Data Bus Activation Timing
Tx
BCLK
Tx
Tx
t41
HOLD
HLDA
18219-59
HOLD Inactive Timing
AM79C965A
199
SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE
EESK
EECS
EEDI
0
1
1
0
A5
A4
A3
A2
A1
A0
EEDO
D15
D14
D13
D2
D3
D0
SHFBUSY
Falling transition on SHFBUSY after 17th word read if the checksum adjust byte in byte 1Fh of EEPROM is correct.
18219-60
Automatic EEPROM Read Functional Timing
t43
EESK
t44
t47
t48 t45
EEDO
Stable
t46
EECS
EEDI
SHFBUSY
18219-61
Automatic EEPROM Read Timing
200
AM79C965A
SWITCHING WAVEFORMS: 10BASE-T INTERFACE
tTR TXD+
tTF tTETD
TXP+
TXD-
TXP-
XMT
18219-62
Transmit Timing
tPWPLP TXD+
TXP+
TXD-
TXPtPWLP tPERLP
18219-63
Idle Link Test Pulse
AM79C965A
201
SWITCHING WAVEFORMS: 10BASE-T INTERFACE
VTSQ+ VTHS+ RXD VTHS- VTSQ-
18219-64
Receive Thresholds (LRT = 0)
VLTSQ+ VLTHS+ RXD VLTHS- VLTSQ-
18219-65
Receive Threshold (LRT = 1)
202
AM79C965A
SWITCHING WAVEFORMS: AUI
tX1H XTAL1 tXI tX1L tX1F tX1R
ISTDCLK (Note 1) ITXEN (Note 1) ITXDAT+ (Note 1) DO+
1 0
1
1 0 tDOTR tDOTF
1
DO-
DO
1
Note 1: Note 1: Internal signal and is shown for clarification only. Transmit Timing--Start of Packet
18219-66
XTAL1
ISTDCLK (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ 1 0 0
DO-
DO
1 Bit (n-2)
0
0 Bit (n)
tDOETD Typical > 200 ns
Bit (n-1)
Note 1: Internal signal and is shown for clarification only. Transmit Timing--End of Packet (Last Bit = 0)
18219-67
AM79C965A
203
SWITCHING WAVEFORMS: AUI
XTAL1
ISTDCLK (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ 1 0 1
DO-
DO 1 Bit (n-2) 0 Bit (n-1) Bit (n)
tDOETD Typical > 250 ns
Note 1: Internal signal and is shown for clarification only. Transmit Timing--End of Packet (Last Bit = 1)
18219-68
204
AM79C965A
SWITCHING WAVEFORMS: AUI
tPWKDI
DI+/- VASQ tPWKDI tPWODI
18219-69
Receiving Timing Diagram
tPWKCI CI+/- VASQ tPWOCI
tPWKCI
18219-70
Collision Timing Diagram
tDOETD
DO+/-
40 mV 100 mV max.
0V
80 Bit Times
18219-71
Port DO ETD Waveform
AM79C965A
205
SWITCHING WAVEFORMS: GPSI
(First Bit Preamble)
(Last Bit )
t GPT1
Transmit Clock (STDCLK)
t GPT2
t GPT3
Transmit Data (TXDAT) Transmit Enable (TXEN) Carrier Present (RXCRS) (Note 1) Collision (CLSN) (Note 2)
t GPT3
t GPT3
t GPT4 t GPT5 t GPT9 t GPT6 t GPT7 t GPT8
Notes: 1. If RXCRS is not present during transmission, LCAR bit in TMD2 will be set. 2. If CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.
18219-72
Transmit Timing
(First Bit Preamble)
(Address Type Designation Bit) (Last Bit)
tGPR1 tGPR2
Receive Clock (SRDCLK) Receive Data (RXDAT) Carrier Present (RXCRS) Collision (CLSN), Active Collision (CLSN), Inactive
tGPR3
tGPR4
tGPR5
tGPR5
tGPR4 tGPR8 tGPR7 tGPR9
tGPR6
tGPR10
tGPR11
(No Collision)
tGPR12
18219-73
Receive Timing
206
AM79C965A
SWITCHING WAVEFORMS: EADI
Preamble SRDCLK
Data Field
SRD tEAD1
One Zero One
SFD
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
Bit 8 Bit 0
Bit 7 Bit 8
tEAD2
SF/BD
tEAD4
tEAD3
tEAD3 Accept tEAD5 Reject tEAD6
18219-74
EAR
EADI Reject Timing
AM79C965A
207
PHYSICAL DIMENSIONS*
PQR160
Plastic Quad Flat Pack Trimmed and Formed
PQR 160
Dwg Rev AA; 08/00
208
AM79C965A
APPENDIX A
PCnet-32 Compatible Media Interface Modules
PCNET-32 COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS
The table below provides a sample list of PCnet-32 compatible 10BASE-T filter and transformer modules available from various vendors. Contact the respective manufacturer for a complete and updated listing of components.
Manufacturer
Part No.
Package
Filters and Transformers
Filters Transformers and Choke
Filters Transformers Dual Choke
Filters Transformers Dual Chokes
Bel Fuse Bel Fuse Bel Fuse Bel Fuse Halo Electronics Halo Electronics Halo Electronics PCA Electronics PCA Electronics PCA Electronics Pulse Engineering Pulse Engineering Pulse Engineering Pulse Engineering Valor Electronics Valor Electronics
A556-2006-DE 0556-2006-00 0556-2006-01 0556-6392-00 FD02-101G FD12-101G FD22-101G EPA1990A EPA2013D EPA2162 PE-65421 PE-65434 PE-65445 PE-65467 PT3877 FL1043
16-pin 0.3" DIL 14-pin SIP 14-pin SIP 16-pin 0.5" DIL 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin 0.3" SIP 16-pin 0.3" DIL 16-pin 0.3" SIL 16-pin 0.3" DIL 12-pin 0.5" SMT 16-pin 0.3" DIL 16-pin 0.3" DIL

PCnet-32 Compatible AUI Isolation Transformers
The table below provides a sample list of PCnet-32 compatible AUI isolation transformers available from various vendors. Contact the respective manufacturer for a complete and updated listing of components.
Manufacturer Bel Fuse Bel Fuse Halo Electronics Halo Electronics PCA Electronics Pulse Engineering Pulse Engineering Valor Electronics Valor Electronics Part No. A553-0506-AB S553-0756-AE TD01-0756K TG01-0756W EP9531-4 PE64106 PE65723 LT6032 ST7032 Package 16-pin 0.3" DIL 16-pin 0.3" SMD 16-pin 0.3" DIL 16-pin 0.3" SMD 16-pin 0.3" DIL 16-pin 0.3" DIL 16-pin 0.3" SMT 16-pin 0.3" DIL 16-pin 0.3" SMD Description 50 H 75 H 75 H 75 H 50 H 50 H 75 H 75 H 75 H
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PCnet-32 Compatible DC/DC Converters
The table below provides a sample list of PCnet-32 compatible DC/DC converters available from various vendors. Contact the respective manufacturer for a complete and updated listing of components.
Manufacturer Halo Electronics Halo Electronics PCA Electronics PCA Electronics PCA Electronics Valor Electronics Valor Electronics Part No. DCU0-0509D DCU0-0509E EPC1007P EPC1054P EPC1078 PM7202 PM7222 Package 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP Voltage 5/-9 5/-9 5/-9 5/-9 5/-9 5/-9 5/-9 Remote On/Off No Yes No Yes Yes No Yes
MANUFACTURER CONTACT INFORMATION
Contact the following companies for further information on their products:
Company Bel Fuse Phone: FAX: Phone: FAX: Phone: FAX: Phone: FAX: Phone: FAX:
U.S. and Domestic (201) 432-0463 (201) 432-9542 (415) 969-7313 (415) 367-7158 (818)-892-0761 (818)-894-5791 (619) 674-8100 (619) 675-8262 (619) 537-2500 (619) 537-2525
Asia 852-328-5515 852-352-3706 65-285-1566 65-284-9466 852-553-0165 852-873-1550 852-425-1651 852-480-5974 852-513-8210 852-513-8214
Europe 33-1-69410402 33-1-69413320
Halo Electronics
PCA Electronics (HPC in Hong Kong) Pulse Engineering
33-1-44894800 33-1-42051579 353-093-24107 353-093-24459 49-89-6923122 49-89-6926542
Valor Electronics
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APPENDIX B
Recommendation for Power and Ground Decoupling
The mixed analog/digital circuitry in the PCnet-32 make it imperative to provide noise-free power and ground connections to the device. Without clean power and ground connections, a design may suffer from high bit error rates or may not function at all. Hence, it is highly recommended that the guidelines presented here are followed to ensure a reliable design. Decoupling/Bypass Capacitors: Adequate decoupling of the power and ground pins and planes is required by all PCnet-32 designs. This includes both low-frequency bulk capacitors and high frequency capacitors. It is recommended that at least one low-frequency bulk (e.g. 22 F) decoupling capacitor be used in the area of the PCnet-32 device. The bulk capacitor(s) should be connected directly to the power and ground planes. In addition, at least 8 high frequency decoupling capacitors (e.g. 0.1 F multilayer ceramic capacitors) should be used around the periphery of the PCnet-32 device to prevent power and ground bounce from affecting device operation. To reduce the inductance between the power and ground pins and the capacitors, the pins should be connected directly to the capacitors, rather than through the planes to the capacitors. The suggested connection scheme for the capacitors is shown in the figure below. Note also that the traces connecting these pins to the capacitors should be as wide as possible to reduce inductance (15 mils is desirable). The most critical pins in the layout of a PCnet-32 design are the 4 analog power and 2 analog ground pins, AVDD[1-4] and AVSS[1-2], respectively. All of these pins are located in one corner of the device, the "analog corner". Specific functions and layout requirements of the analog power and ground pins are given below. AVSS1 and AVDD3: These pins provide the power and ground for the Twisted Pair and AUI drivers. In addition AVSS1 serves as the ground for the logic interfaces in the 20 MHz Crystal Oscillator. Hence, these pins can be very noisy. A dedicated 0.1 F capacitor between these pins is recommended. AVSS2 and AVDD2: These pins are the most critical pins on the PCnet-32 device because they provide the power and ground for the phase-lock loop (PLL) portion of the chip. The voltage-controlled oscillator (VCO) portion of the PLL is sensitive to noise in the 60 kHz - 200 kHz range. To prevent noise in this frequency range from disrupting the VCO, it is strongly recommended that the low-pass filter shown below be implemented on these pins.
VDD plane
33 F to 10 F
AVDD2 1 to 10
Via to the Power Plane
PCnetTM
AVSS2
Vdd C A P PCnet Vss C A P
Vdd PCnet Vss C A P
Vdd PCnet Vss
VSS plane
To determine the value for the resistor and capacitor, the formula is: R * C 88
Via to the Ground Plane Correct Correct Incorrect
where R is in ohms and C is in microfarads. Some possible combinations are given below. To minimize the voltage drop across the resistor, the R value should not be more than 10 .
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R 2.7 4.3 6.8 10
C 33 F 22 F 15 F 10 F
AVDD1: AVDD1 provides power for the control and interface logic in the PLL. Ground for this logic is provided by digital ground pins. No specific decoupling is necessary on this pin. Special Note for Adapter Cards: In adapter card designs, it is important to utilize all available power and ground pins available on the bus edge connector. In addition, the connection from the bus edge connector to the power or ground plane should be made through more than one via and with wide traces (15 mils desirable) wherever possible. Following these recommendations results in minimal inductance in the power and ground paths. By minimizing this inductance, ground bounce is minimized.
AVSS2 and AVDD2/AVDD4: These pins provide power and ground for the AUI and twisted pair receive circuitry. In addition, as mentioned earlier, AVSS2 and AVDD2 provide power and ground for the phase-lock loop portion of the chip. Except for the filter circuit already mentioned, no specific decoupling is necessary on these pins.
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APPENDIX C
Alternative Method for Initialization
The PCnet-32 controller may be initialized by performing I/O writes only. That is, data can be written directly to the appropriate control and status registers (CSR) instead of reading from the Initialization Block in memory. The registers that must be written are shown in the table below. These books are followed by writing the START bit in CSR0.
Control and Status Register CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR24-25 CSR30-31 CSR47 CSR76 CSR78
Comment LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] PADR[15:0] PADR[31:16] PADR[47:32] Mode BADR BADX POLLINT RCVRL XMTRL
Note: The INIT bit must not be set or the initialization block will be accessed instead.
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APPENDIX D
Introduction of the Look-Ahead Packet Processing (LAPP) Concept
A driver for the PCnet-32 controller would normally require that the CPU copy receive frame data from the controller's buffer space to the application's buffer space after the entire frame has been received by the controller. For applications that use a ping-pong windowing style, the traffic on the network will be halted until the current frame has been completely processed by the entire application stack. This means that the time between last byte of a receive frame arriving at the client's Ethernet controller and the client's transmission of the first byte of the next outgoing frame will be separated by: 1. the time that it takes the client's CPU's interrupt procedure to pass software control from the current task to the driver 2. plus the time that it takes the client driver to pass the header data to the application and request an application buffer 3. plus the time that it takes the application to generate the buffer pointer and then return the buffer pointer to the driver 4. plus the time that it takes the client driver to transfer all of the frame data from the controller's buffer space into the application's buffer space and then call the application again to process the complete frame 5. plus the time that it takes the application to process the frame and generate the next outgoing frame 6. plus the time that it takes the client driver to set up the descriptor for the controller and then write a TDMD bit to CSR0 The sum of these times can often be about the same as the time taken to actually transmit the frames on the wire, thereby yielding a network utilization rate of less than 50%. An important thing to note is that the PCnet-32 controller's data transfers to its buffer space are such that the system bus is needed by the PCnet-32 controller for approximately 4% of the time. This leaves 96% of the sytem bus bandwidth for the CPU to perform some of the inter-frame operations in advance of the completion of network receive activity, if possible. The question then becomes: how much of the tasks that need to be performed between reception of a frame and transmission of the next frame can be performed before the reception of the frame actually ends at the network, and how can the CPU be instructed to perform these tasks during the network reception time? The answer depends upon exactly what is happening in the driver and application code, but the steps that can be performed at the same time as the receive data are arriving include as much as the first three steps and part of the fourth step shown in the sequence above. By performing these steps before the entire frame has arrived, the frame throughput can be substantially increased. A good increase in performance can be expected when the first three steps are performed before the end of the network receive operation. A much more significant performance increase could be realized if the PCnet-32 controller could place the frame data directly into the application's buffer space; (i.e. eliminate the need for step four.) In order to make this work, it is necessary that the application buffer pointer be determined before the frame has completely arrived, then the buffer pointer in the next desriptor for the receive frame would need to be modified in order to direct the PCnet-32 controller to write directly to the application buffer. More details on this operation will be given later. An alternative modification to the existing system can gain a smaller, but still significant improvement in performance. This alternative leaves step four unchanged in that the CPU is still required to perform the copy operation, but it allows a large portion of the copy operation to be done before the frame has been completely received by the controller, (i.e. the CPU can perform the copy operation of the receive data from the PCnet32 controller's buffer space into the application buffer space before the frame data has completely arrived from the network.) This allows the copy operation of step four to be performed concurrently with the arrival of network data, rather than sequentially, following the end of network receive activity.
Outline of the LAPP Flow:
This section gives a suggested outline for a driver that utilizes the LAPP feature of the PCnet-32 controller. Note: The labels in the following text are used as references in the timeline diagram that follows.
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SETUP:
The driver should set up descriptors in groups of 3, with the OWN and STP bits of each set of three descriptors to read as follows: 11b, 10b, 00b. An option bit (LAPPEN) exists in CSR3, bit position 5. The software should set this bit. When set, the LAPPEN bit directs the PCnet-32 controller to generate an INTERRUPT when STP has been written to a receive descriptor by the PCnet-32 controller.
space. Only when the message does not fit will it signal a buffer error condition - there is no need to panic at the point that it discovers that it does not yet own descriptor number 3.] S2: The first task of the driver's interrupt service routine is to collect the header information from the PCnet32 controller's first buffer and pass it to the application. S3: The application will return an application buffer pointer to the driver. The driver will add an offset to the application data buffer pointer, since the PCnet-32 controller will be placing the first portion of the message into the first and second buffers. (The modified application data buffer pointer will only be directly used by the PCnet-32 controller when it reaches the third buffer.) The driver will place the modified data buffer pointer into the final descriptor of the group (#3) and will grant ownership of this descriptor to the PCnet-32 controller. C5: Interleaved with S2, S3 and S4 driver activity, the PCnet-32 controller will write frame data to buffer number 2. S4: The driver will next proceed to copy the contents of the PCnet-32 controller's first buffer to the beginning of the application space. This copy will be to the exact (unmodified) buffer pointer that was passed by the application. S5: After copying all of the data from the first buffer into the beginning of the application data buffer, the driver will begin to poll the ownership bit of the second descriptor. The driver is waiting for the PCnet-32 controller to finish filling the second buffer. C6: At this point, knowing that it had not previously owned the third descriptor, and knowing that the current message has not ended (there is more data in the fifo), the PCnet-32 controller will make a "last ditch look-ahead" to the final (third) descriptor; This time, the ownership will be TRUE (i.e. the descriptor belongs to the controller), because the driver wrote the application pointer into this descriptor and then changed the ownership to give the descriptor to the PCnet-32 controller back at S3. Note that if steps S1, S2 and S3 have not completed at this time, a BUFF error will result. C7: After filling the second buffer and performing the last chance look-ahead to the next descriptor, the PCnet-32 controller will write the status and change the ownership bit of descriptor number 2. S6: After the ownership of descriptor number 2 has been changed by the PCnet-32 controller, the next driver poll of the 2nd descriptor will show ownership granted to the CPU. The driver now copies the data from buffer number 2 into the "middle section"
FLOW:
The PCnet-32 controller polls the current receive descriptor at some point in time before a message arrives. The PCnet-32 controller determines that this receive buffer is OWNed by the PCnet-32 controller and it stores the descriptor information to be used when a message does arrive. N0: Frame preamble appears on the wire, followed by SFD and destination address. N1: The 64th byte of frame data arrives from the wire. This causes the PCnet-32 controller to begin frame data DMA operations to the first buffer. C0: When the 64th byte of the message arrives, the PCnet-32 controller performs a look-ahead operation to the next receive descriptor. This descriptor should be owned by the PCnet-32 controller. C1: The PCnet-32 controller intermittently requests the bus to transfer frame data to the first buffer as it arrives on the wire. S0: The driver remains idle. C2: When the PCnet-32 controller has completely filled the first buffer, it writes status to the first descriptor. C3: When the first descriptor for the frame has been written, changing ownership from the PCnet-32 controller to the CPU, the PCnet-32 controller will generate an SRP INTERRUPT. (This interrupt appears as a RINT interrupt in CSR0.) S1: The SRP INTERRUPT causes the CPU to switch tasks to allow the PCnet-32 controller's driver to run. C4: During the CPU interrupt-generated task switching, the PCnet-32 controller is performing a lookahead operation to the third descriptor. At this point in time, the third descriptor is owned by the CPU. [Note: Even though the third buffer is not owned by the PCnet-32 controller, existing AMD Ethernet controllers will continue to perform data DMA into the buffer space that the controller already owns (i.e. buffer number 2). The controller does not know if buffer space in buffer number 2 will be sufficient or not, for this frame, but it has no way to tell except by trying to move the entire message into that
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of the application buffer space. This operation is interleaved with the C7 and C8 operations. C8: The PCnet-32 controller will perform data DMA to the last buffer, whose pointer is pointing to application space. Data entering the last buffer will not need the infamous "double copy" that is required by existing drivers, since it is being placed directly into the application buffer space. N2: The message on the wire ends. S7: When the driver completes the copy of buffer number 2 data to the application buffer space, it begins polling descriptor number 3.
C9: When the PCnet-32 controller has finished all data DMA operations, it writes status and changes ownership of descriptor number 3. S8: The driver sees that the ownership of descriptor number 3 has changed, and it calls the application to tell the application that a frame has arrived. S9: The application processes the received frame and generates the next TX frame, placing it into a TX buffer. S10:The driver sets up the TX descriptor for the PCnet-32 controller.
Ethernet Wire activity:
Ethernet Controller activity:
Software activity:
S10: Driver sets up TX descriptor. S9: Application processes packet, generates TX packet. S8: Driver calls application to tell application that packet has arrived. S7: Driver polls descriptor of buffer #3.
C9: Controller writes descriptor #3. N2: EOM C8: Controller is performing intermittent bursts of DMA to fill data buffer #3. C7: Controller writes descriptor #2. C6: "Last chance" lookahead to descriptor #3 (OWN). Buffer #3
{
S6: Driver copies data from buffer #2 to the application buffer.
S5: Driver polls descriptor #2.
S4: Driver copies data from buffer #1 to the application buffer. C5: Controller is performing intermittent bursts of DMA to fill data buffer #2. Buffer #2 C4: Lookahead to descriptor #3 (OWN). C3: SRP interrupt is generated.
}{
S1: Interrupt latency.
S3: Driver writes modified application pointer to descriptor #3. S2: Driver call to application to get application buffer pointer.
packet data arriving
}
C2: Controller writes descriptor #1.
C1: Controller is performing intermittent bursts of DMA to fill data buffer #1.
Buffer #1
S0: Driver is idle.
{
C0: Lookahead to descriptor #2. N1: 64th byte of packet data arrives.
N0: Packet preamble, SFD and destination address are arriving.
18219-76
Figure 1. LAPP Timeline
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LAPP Software Requirements
Software needs to set up a receive ring with descriptors formed into groups of 3. The first descriptor of each group should have OWN = 1 and STP = 1, the second descriptor of each group should have OWN = 1 and STP = 0. The third descriptor of each group should have OWN = 0 and STP = 0. The size of the first buffer (as indicated in the first descriptor), should be at least equal to the largest expected header size; However, for maximum efficiency of CPU utilization, the first buffer size should be larger than the header size. It should be equal to the expected number of message bytes, minus the time needed for Interrupt latency and minus the application call latency, minus the time needed for the driver to write to the third descriptor, minus the time needed for the driver to copy data from buffer #1 to the application buffer space, and minus the time needed for the driver to copy data from buffer #2 to the application buffer space. Note that the time needed for the copies performed by the driver depends upon the sizes of the 2nd and 3rd buffers, and that the sizes of the second and third buffers need to be set according to the time needed for the data copy operations! This means that an iterative self-adjusting mechanism needs to be placed into the software to determine the correct buffer sizing for optimal operation. Fixed values for buffer sizes may be used; In such a case, the LAPP method will still provide a significant performance increase, but the performance increase will not be maximized. The following diagram illustrates this setup for a receive ring size of 9:
LAPP Rules for Parsing of Descriptors
When using the LAPP method, software must use a modified form of descriptor parsing as follows: Software will examine OWN and STP to determine where a RCV frame begins. RCV frames will only begin in buffers that have OWN = 0 and STP = 1. Software shall assume that a frame continues until it finds either ENP = 1 or ERR= 1. Software must discard all descriptors with OWN = 0 and STP = 0 and move to the next descriptor when searching for the beginning of a new frame; ENP and ERR should be ignored by software during this search. Software cannot change an STP value in the receive descriptor ring after the initial setup of the ring is complete, even if software has ownership of the STP descriptor unless the previous STP descriptor in the ring is also OWNED by the software. When LAPPEN = 1, then hardware will use a modified form of descriptor parsing as follows: The controller will examine OWN and STP to determine where to begin placing a RCV frame. A new RCV frame will only begin in a buffer that has OWN = 1 and STP = 1. The controller will always obey the OWN bit for determining whether or not it may use the next buffer for a chain. The controller will always mark the end of a frame with either ENP = 1 or ERR = 1.
Descriptor #9 Descriptor #8 Descriptor #7 Descriptor #6 Descriptor #5 Descriptor #4 Descriptor #3 Descriptor #2 Descriptor #1
OWN = 0 STP = 0 SIZE = S6 OWN = 1 STP = 0 SIZE = S1+S2+S3+S4 OWN = 1 STP = 1 SIZE = A-(S1+S2+S3+S4+S6) OWN = 0 STP = 0 SIZE = S6 OWN = 1 STP = 0 SIZE = S1+S2+S3+S4 OWN = 1 STP = 1 SIZE = A-(S1+S2+S3+S4+S6) OWN = 0 STP = 0 SIZE = S6 OWN = 1 STP = 0 SIZE = S1+S2+S3+S4 OWN = 1 STP = 1 SIZE = A-(S1+S2+S3+S4+S6)
A = Expected message size in bytes S1 = Interrupt latency S2 = Application call latency S3 =Time needed for driver to write to third descriptor S4 = Time needed for driver to copy data from buffer #1 to application buffer space S6 = Time needed for driver to copy data from buffer #2 to application buffer space Note that the times needed for tasks S1, S2, S3, S4, and S6 should be divided by 0.8 microseconds to yield an equivalent number of network byte times before subtracting these quantities from the expected message size A.
18219-77
Figure 2. LAPP 3 Buffering Grouping
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The controller will discard all descriptors with OWN = 1 and STP = 0 and move to the next descriptor when searching for a place to begin a new frame. It discards these desciptors by simply changing the ownership bit from OWN=1 to OWN = 0. Such a descriptor is unused for receive purposes by the controller, and the driver must recognize this. (The driver will recognize this if it follows the software rules.) The controller will ignore all descriptors with OWN = 0 and STP = 0 and move to the next descriptor when searching for a place to begin a new frame. In other words, the controller is allowed to skip entries in the
ring that it does not own, but only when it is looking for a place to begin a new frame.
Some Examples of LAPP Descriptor Interaction
Choose an expected frame size of 1060 bytes. Choose buffer sizes of 800, 200 and 200 bytes. 1. Assume that a 1060 byte frame arrives correctly, and that the timing of the early interrupt and the software is smooth. The descriptors will have changed from:
Descriptor Number OWN 1 2 3 4 5 6 etc. 1 1 0 1 1 0 1
Before the Frame Arrived STP 1 0 0 1 0 0 1 ENP* X X X X X X X
After the Frame has Arrived
Comments (After Frame Arrival)
OWN 0 0 0 1 1 0 1
STP 1 0 0 1 0 0 1
ENP* 0 0 1 X X X X Bytes 1-800 Bytes 801-1000 Bytes 1001-1060 Controller's current location Not yet used Not yet used Not yet used
* ENP or ERR
2. Assume that instead of the expected 1060 byte frame, a 900 byte frame arrives, either because
there was an error in the network, or because this is the last frame in a file transmission sequence.
Descriptor Number OWN 1 2 3 4 5 6 etc. 1 1 0 1 1 0 1
Before the Frame Arrived STP 1 0 0 1 0 0 1 ENP* X X X X X X X OWN 0 0 0 1 1 0 1
After the Frame has Arrived STP 1 0 0 1 0 0 1 ENP* 0 1 ?** X X X X
Comments (After Frame Arrival)
Bytes 1-800 Bytes 801-900 Discarded buffer Controller's current location Not yet used Not yet used Not yet used
*ENP or ERR ** Note that the PCnet-32 controller might write a ZERO to ENP location in the 3rd descriptor. Here are the two possibilities: 1) If the controller finishes the data transfers into buffer number 2 after the driver writes the application's modified buffer pointer into the third descriptor, then the controller will write a ZERO to ENP for this buffer and will write a ZERO to OWN and STP. 2) If the controller finishes the data transfers into buffer number 2 before the driver writes the application's modified buffer pointer into the third descriptor, then the controller will complete the frame in buffer number two and then skip the then unowned third buffer. In this case, the PCnet-32 controller will not have had the opportunity to RESET the ENP bit in this descriptor, and it is possible that the software left this bit as ENP=1 from the last time through the ring. Therefore, the software
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must treat the location as a don't care; The rule is, after finding ENP=1 (or ERR=1) in descriptor number 2, the software must ignore ENP bits until it finds the next STP=1.
3. Assume that instead of the expected 1060 byte frame, a 100 byte frame arrives, because there was an error in the network, or because this is the last
Descriptor Number OWN 1 2 3 4 5 6 etc. 1 1 0 1 1 0 1 Before the Frame Arrived STP 1 0 0 1 0 0 1 ENP* X X X X X X X OWN 0 0 0 1 1 0 1
frame in a file transmission sequence, or perhaps because it is an acknowledge frame.
After the Frame has Arrived STP 1 0 0 1 0 0 1 ENP* 1 0*** ?** X X X X
Comments (After Frame Arrival)
Bytes 1-100 Discarded buffer Discarded buffer Controller's current location Not yet used Not yet used Not yet used
* ENP or ERR ** Same as note in case 2 above, except that in this case, it is very unlikely that the driver can respond to the interrupt and get the pointer from the application before the PCnet-32 controller has completed its poll of the next descriptors. This means that for almost all occurrences of this case, the PCnet-32 controller will not find the OWN bit set for this descriptor and therefore, the ENP bit will almost always contain the old value, since the PCnet-32 controller will not have had an opportunity to modify it. *** Note that even though the PCnet-32 controller will write a ZERO to this ENP location, the software should treat the location as a don't care, since after finding the ENP=1 in descriptor number 2, the software should ignore ENP bits until it finds the next STP=1.
Buffer Size Tuning
For maximum performance, buffer sizes should be adjusted depending upon the expected frame size and the values of the interrupt latency and application call latency. The best driver code will minimize the CPU utilization while also minimizing the latency from frame end on the network to frame sent to application from driver (frame latency). These objectives are aimed at increasing throughput on the network while decreasing CPU utilization. Note that the buffer sizes in the ring may be altered at any time that the CPU has ownership of the corresponding descriptor. The best choice for buffer sizes will maximize the time that the driver is swapped out, while minimizing the time from the last byte written by the PCnet-32 controller to the time that the data is passed from the driver to the application. In the diagram, this corresponds to maximizing S0, while minimizing the time between C9 and S8. (The timeline happens to show a minimal time from C9 to S8.) Note that by increasing the size of buffer number 1, we increase the value of S0. However, when we increase the size of buffer number 1, we also increase the value of S4. If the size of buffer number 1 is too large, then the driver will not have enough time to perform tasks S2, S3, S4, S5 and S6. The result is that there will be delay from the execution of task C9 until the execution of task S8. A perfectly timed system will have the values for S5 and S7 at a minimum. An average increase in performance can be achieved if the general guidelines of buffer sizes in figure 2 is followed. However, as was noted earlier, the correct sizing for buffers will depend upon the expected message size. There are two problems with relating expected message size with the correct buffer sizing: 1. Message sizes cannot always be accurately predicted, since a single application may expect different message sizes at different times, therefore, the buffer sizes chosen will not always maximize throughput. 2. Within a single application, message sizes might be somewhat predictable, but when the same driver is to be shared with multiple applications, there may not be a common predictable message size. Additional problems occur when trying to define the correct sizing because the correct size also depends
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upon the interrupt latency, which may vary from system to system, depending upon both the hardware and the software installed in each system. In order to deal with the unpredictable nature of the message size, the driver can implement a self-tuning mechanism that examines the amount of time spent in tasks S5 and S7 as such: While the driver is polling for each descriptor, it could count the number of poll operations performed and then adjust the number 1 buffer size to a larger value, by adding "t" bytes to the buffer count, if the number of poll operations was greater than "x". If fewer than "x" poll operations were needed for each of S5 and S7, then the software should adjust the buffer size to a smaller value by, subtracting "y" bytes from the buffer count. Experiments with such a tuning mechanism must be performed to determine the best values for "X" and "y." Note whenever the size of buffer number 1 is adjusted, buffer sizes for buffer number 2 and buffer 3 should also be adjusted. In some systems the typical mix of receive frames on a network for a client application consists mostly of large data frames, with very few small frames. In this case, for maximum efficiency of buffer sizing, when a frame arrives under a certain size limit, the driver should not adjust the buffer sizes in response to the short frame. An Alternative LAPP Flow - the TWO Interrupt Method An alternative to the above suggested flow is to use two interrupts, one at the start of the Receive frame and the other at the end of the receive frame, instead of just looking for the SRP interrupt as was described above. This alternative attempts to reduce the amount of time that the software "wastes" while polling for descriptor own bits. This time would then be available for other CPU tasks. It also minimizes the amount of time the
CPU needs for data copying. This savings can be applied to other CPU tasks. The time from the end of frame arrival on the wire to delivery of the frame to the application is labeled as frame latency. For the one-interrupt method, frame latency is minimized, while CPU utilization increases. For the two-interrupt method, frame latency becomes greater, while CPU utilization decreases. Note that some of the CPU time that can be applied to non-Ethernet tasks is used for task switching in the CPU. One task switch is required to swap a non-Ethernet task into the CPU (after S7A) and a second task switch is needed to swap the Ethernet driver back in again (at S8A). If the time needed to perform these task switches exceeds the time saved by not polling descriptors, then there is a net loss in performance with this method. Therefore, the SPRINT method implemented should be carefully chosen. Figure 3 shows the event flow for the two-interrupt method. Figure 4 shows the buffer sizing for the two-interrupt method. Note that the second buffer size will be about the same for each method. There is another alternative which is a marriage of the two previous methods. This third possibility would use the buffer sizes set by the two-interrupt method, but would use the polling method of determining frame end. This will give good frame latency but at the price of very high CPU utilization. And still, there are even more compromise positions that use various fixed buffer sizes and effectively, the flow of the one-interrupt method. All of these compromises will reduce the complexity of the one-interrupt method by removing the heuristic buffer sizing code, but they all become less efficient than heuristic code would allow.
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Ethernet Wire activity:
Ethernet Controller activity:
Software activity:
S10: Driver sets up TX descriptor. S9: Application processes packet, generates TX packet. S8: Driver calls application to tell application that packet has arrived. S8A: Interrupt latency.
{
C10: ERP interrupt is generated. C9: Controller writes descriptor #3. C8: Controller is performing intermittent bursts of DMA to fill data buffer #3. N2: EOM C7: Controller writes descriptor #2. C6: "Last chance" lookahead to descriptor #3 (OWN). Buffer #3
}
S7: Driver is swapped out, allowing a non-Etherenet application to run. S7A: Driver Interrupt Service Routine executes RETURN. S6: Driver copies data from buffer #2 to the application buffer.
{
S5: Driver polls descriptor #2.
S4: Driver copies data from buffer #1 to the application buffer. C5: Controller is performing intermittent bursts of DMA to fill data buffer #2. Buffer #2 C4: Lookahead to descriptor #3 (OWN). C3: SRP interrupt is generated.
}{
S1: Interrupt latency.
S3: Driver writes modified application pointer to descriptor #3. S2: Driver call to application to get application buffer pointer.
packet data arriving
}
C2: Controller writes descriptor #1.
C1: Controller is performing intermittent bursts of DMA to fill data buffer #1.
Buffer #1
S0: Driver is idle.
C0: Lookahead to descriptor #2.
{
N1: 64th byte of packet data arrives.
N0: Packet preamble, SFD and destination address are arriving.
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Figure 3. LAPP Timeline for TWO-INTERRUPT Method
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Descriptor #9 Descriptor #8 Descriptor #7 Descriptor #6 Descriptor #5 Descriptor #4 Descriptor #3 Descriptor #2 Descriptor #1
OWN = 0 STP = 0 SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE) OWN = 1 SIZE = S1+S2+S3+S4 STP = 0
OWN = 1 STP = 1 SIZE = HEADER_SIZE (minimum 64 bytes) OWN = 0 STP = 0 SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE) OWN = 1 SIZE = S1+S2+S3+S4 STP = 0
A = Expected message size in bytes S1 = Interrupt latency S2 = Application call latency S3 =Time needed for driver to write to third descriptor S4 = Time needed for driver to copy data from buffer #1 to application buffer space S6 = Time needed for driver to copy data from buffer #2 to application buffer space Note that the times needed for tasks S1, S2, S3, S4, and S6 should be divided by 0.8 microseconds to yield an equivalent number of network byte times before subtracting these quantities from the expected message size A.
OWN = 1 STP = 1 SIZE = HEADER_SIZE (minimum 64 bytes) OWN = 0 STP = 0 SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE) OWN = 1 SIZE = S1+S2+S3+S4 STP = 0
OWN = 1 STP = 1 SIZE = HEADER_SIZE (minimum 64 bytes)
18219-79
Figure 4. LAPP 3 Buffer Grouping for TW0-INTERRUPT Method
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APPENDIX E
AM79C965A PCnet-32 Silicon Errata Report
AM 79C965A REV B1 SILICON STATUS
The items below are the known errata for Rev B1 silicon. Rev B1 silicon is the production silicon. Note: A signal followed by "*" indicates active low; i.e., Master*. The "Description" section of this document gives an external description of the problem. The "Implication" section gives an explanation of how to PCnet-ISA II controller behaves and its impact on the system. The "Work-around" section describes a work-around for the problem. The "Status" section describes when and how the problem will be corrected. Current package marking for this revision:
Line 1: Line 2: AM79C965AKC (Assuming package is PQFP) Line 3: B1 Line 4: (c) 1993 AMD
Value of chip ID registers CSR89+CSR88 [31:0] for this revision = 32430003h. (When read in 16-bit mode.) 1. Incorrect interpretation of descriptor ring length in 32-bit software mode Description: In 32-bit software mode, if TLEN and RLEN is set to 8 hex, indicating a descriptor ring length of 256 in the INIT block, the PCnet-32 controller will internally interpret ring length to be 512. Also, if TLEN or RLEN is set to C hex, the PCnet-32 controller converts it to 256 instead of 512. The table below summarizes the corresponding TLEN/RLEN settings and their actual interpretations.
TLEN or RLEN Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
Correct Ring Length 1 2 4 8 16 32 64 128 256 512 512 512 512 512 512 512
Erratum Ring Length 1 2 4 8 16 32 64 128 512 *Bad 512 512 512 256 *Bad 512 512 512
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Implication: There is no jeopardy to customers using AMD drivers, because AMD OS drivers do not use ring lengths that long. For customers developing proprietary drivers, implementation of the following work-around is highly recommended. Work-around: 1. Program TLEN or RLEN to C hex if ring length of 256 is desired, or 2. - Initialize INIT block with any value for TLEN or RLEN - Set INIT, don't set STRT - After IDON, set STOP - Write to CSR76 (RCVRL) and CSR78 (XMTRL) with correct value -Set STRT Status: No current plan to revise silicon to fix this erratum. 2. Receive Frame Align feature not functioning correctly Description: The Receive Frame Align feature does not function correctly. The data field of a received frame will not necessarily be forced to align to a double-word aligned address boundary when the RCVALGN bit (bit 0) in CSR122 is set. Two extra bytes will not always be inserted at the beginning of the receive packet destination address field. Implication: Users are not able to force the data field of 802.3 frames to align to 0 MOD 4 address boundaries, i.e. double-word aligned addresses, by setting this bit. Work-around: None. Do not activate this bit. This feature of the device does not function as described in the data sheet. Status: No current plan to revise silicon to fix this erratum. 3. False BABL errors generated Description: The PCnet-32 device will intermittently give BABL error indications when the network traffic has frames equal to or greater than 1518 bytes. Implication: False BABL errors on the receiving station can be passed up to the upper layer software if the PCnet-32 device is just coming out of a deferral and the multi-purpose counter used to count the number of bytes received reaches 1518 at the same time. If the network is heavily loaded with full-size frames, the probability of a false BABL error is high. Work-around: There are two possible work-arounds. 1. If the user has no intention to transmit frames larger than 1518 bytes, the BABL bit may be masked to ignore babble errors. In this case, the false babble error will not cause an interrupt, nor will it be passed to the higherlevel software. 2. Check to see if the device is transmitting in ISR (Interrupt Service Routine), which is induced by the BABL error. The BCRs that control the LED settings can be programmed to indicate a transmit activity, assuming the interrupt latency is not longer than one minute IFG (Inter-Frame Gap) time.
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If (ISR_LATENCY < 9.6 us) True_bable_err = BABL* (TINT+XMT_LED) { i.e.False_bable_err = ~ (BABL* (TINT+XMT_LET))} else Cannot tell if the BABL error is true or false just by reading BABL, TINT, XMT_LED bits in ISR. Status: No current plan to fix this item.
Enhancement
The Enhancement section gives an external description of the enhancement. The Implication section gives an explanation of how the PCnet-32 ISA behaves and its impact on the system. The Status section indicates when the enhancement will be implemented. 1. Improved Phase Lock Loop function Enhancement: The PLL (Phase Lock Loop) circuit in revision B1 silicon is enhanced to provide better phase tracking. Implication: With this PLL enhancement, the number of potentially dropped packets is effectively zero. Status: Implemented in revision B1 silicon.
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The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
Trademarks Copyright (c) 1998, 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, bIMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST, PCnetFAST+, PCnet-Mobile, QFEX, QFEXr, QuASI, QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc. Microsoft is a registered trademark of Microsoft Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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